Lomash Chandra Acharya, A. Sharma, N. Mishra, Khoirom Johnson Singh, M. Dargupally, N. Gupta, S. S. Nayakanti, A. Mandal, V. Ramakrishnan, S. Dasgupta, and A. Bulusu, “Switching activity factor-based ECSM characterization (SAFE): A novel technique for aging-aware static timing analysis,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024, doi: 10.1109/TCAD.2024.3396432. (Early Access). Article Link
Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, and Sudeb Dasgupta, “Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-based ferroelectric gate stacks and introducing a circuit-compatible hybrid compact model for leakage-aware NCFETs,” Solid-State Electron., vol. 216, Art. No. 108932, Jun. 2024, doi: 10.1016/j.sse.2024.108932. Article Link
Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, and Sudeb Dasgupta, “Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations,” Microelectron. J., vol. 142, Art. No. 105981, Dec. 2023, doi: 10.1016/j.mejo.2023.105981. Article Link
Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, and Sudeb Dasgupta, “Exploring the impact of domain numbers on negative capacitance effects in ferroelectric device-circuit co-design,” Solid-State Electron., vol. 210, Art. No. 108792, Dec. 2023, doi: 10.1016/j.sse.2023.108792. Article Link
Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, M. Dargupally, N. Mishra, A. Sharma, A. Acharya, V. Ramakrishnan, A. Mandal, S. Dasgupta, and A. Bulusu, “Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF,” Solid-State Electron., vol. 210, Art. No. 108790, Dec. 2023, doi: 10.1016/j.sse.2023.108790. Article Link
Lomash Chandra Acharya, A. K. Sharma, N. Mishra, Khoirom Johnson Singh, M. Dargupally, N. S. Shabarish, A. Mandal, V. Ramakrishnan, S. Dasgupta, A. Bulusu, “Aging aware timing model of CMOS inverter: path level timing performance and its impact on the logical effort,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 8, pp. 2657-2663, Aug. 2023, doi: 10.1109/TCAD.2022.3231173. Article Link
Khoirom Johnson Singh, N. Chauhan, Anand Bulusu, and Sudeb Dasgupta, “Physical cause and impact of negative capacitance effect in ferroelectric P(VDF-TrFE) gate stack and its application to Landau transistor,” IEEE Open J. Ultrason. Ferroelectr. Freq. Control, vol. 2, pp. 55–64, 2022, doi: 10.1109/OJUFFC.2022.3172665. Article Link
Khoirom Johnson Singh, Anand Bulusu, and Sudeb Dasgupta, “Understanding negative capacitance physical mechanism in organic ferroelectric capacitor,” Solid-State Electron., vol. 194, Art. No. 108350, Aug. 2022, doi: 10.1016/j.sse.2022.108350. Article Link
Khoirom Johnson Singh, Anand Bulusu, and Sudeb Dasgupta, “Origin of negative capacitance transient in ultrascaled multidomain metal-ferroelectric-metal stack and hysteresis-free Landau transistor,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1284–1292, Mar. 2022, doi: 10.1109/TED.2021.3139057. Article Link
Khoirom Johnson Singh, Anand Bulusu, and Sudeb Dasgupta, “Multidomain negative capacitance effect in P(VDF-TrFE) ferroelectric capacitor and passive voltage amplification,” IEEE Trans. Electron Devices, vol. 67, no. 11, pp. 4696–4700, Nov. 2020, doi: 10.1109/TED.2020.3022745. Article Link
Khoirom Johnson Singh, Tripurari Sharan, and Huirem Tarunkumar, “High speed and low power basic digital logic gates, half-adder and full-adder using modified gate diffusion input technology,” in Journal of VLSI Design Tools and Technology, vol. 8, no. 1, pp. 34–42, Apr. 2018, doi: 10.37591/JOVDTT.V8I1.468. Article Link
M. Dargupally, L. C. Acharya, Khoirom Johnson Singh, N. Gupta, A. Sharma, S. Dasgupta, and A. Bulusu, "An efficient standard cell design methodology by exploiting body biasing and poly biasing in FDSOI for NTV regime," 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Hyderabad, India, 2023, pp. 105-109, doi: 10.1109/APCCAS60141.2023.00034. Article Link
L. C. Acharya, A. Kumar, Khoirom Johnson Singh, N. Gupta, N. S. Shabarish, N. Mishra, M. Dargupally, A. Kumar Sharma, V. Ramakrishnan, A. Mandal, S. Dasgupta, and A. Bulusu, "Beyond SPICE simulation: A novel variability-aware STA methodology for digital timing closure," 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Funchal, Portugal, 2023, pp. 1-4, doi: 10.1109/SMACD58065.2023.10192158. Article Link
Khoirom Johnson Singh, Lomash Chandra Acharya, Mahipal Dargupally, Anand Bulusu, and Sudeb Dasgupta, “Post-CMOS devices: Landau’s anisotropy sensitivity analyses for organic ferroelectric gate stack and its application to NCTFET,” Proc. IEEE Latin Amer. Electron Devices Conf. (LAEDC), Cancun, Mexico, pp. 1–4, Jul. 2022, doi: 10.1109/LAEDC54796.2022.9908182. Article Link
Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, and Sudeb Dasgupta, “Significance of organic ferroelectric in harnessing transient negative capacitance effect at low voltage over oxide ferroelectric,” Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Austin, TX, USA, pp. 3423–3427, May 2022, doi: 10.1109/ISCAS48785.2022.9937975. Article Link
Khoirom Johnson Singh, Anand Bulusu, and Sudeb Dasgupta, “Harnessing maximum negative capacitance signature voltage window in P(VDF-TrFE) gate stack,” Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Daegu, Korea, pp. 1–5, May 2021, doi: 10.1109/ISCAS51556.2021.9401100. Article Link
Khoirom Johnson Singh, Anand Bulusu, and Sudeb Dasgupta, “Ultrascaled multidomain P(VDF-TrFE) organic ferroelectric gate stack to the rescue,” Proc. IEEE Latin Amer. Electron Devices Conf. (LAEDC), Mexico, Mexico, pp. 1–4, Apr. 2021, doi: 10.1109/LAEDC51812.2021.9437926. Article Link
Tripurari Sharan, Khoirom Johnson Singh, and A. K. Gautam, “Current Feedback Operational Amplifier-Based Biquadratic Filter,” in Advances in VLSI, Communication, and Signal Processing: Select Proceedings of VCAS 2018, Dec 2019, vol. 587, pp. 481-495, doi: 10.1007/978-981-32-9775-3_43. Article Link
Inventor in a patent filed on A Method For Obtaining A Negative Capacitance Effect In A Multidomain P(VDF-TrFE) Organic Ferroelectric Capacitor and A Passive Voltage Amplifier Application number: AU2021106165A; Status: Granted. Article Link