Journal papers

1. Yi-Yu Liu, Kuo-Hua Wang, and TingTing Hwang, "Crosstalk minimization in logic synthesis for PLA", in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, I. 4, pp. 890-915, 2006.

2. Yi-Yu Liu and TingTing Hwang, "Crosstalk-aware domino logic synthesis", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, I. 6, pp. 1155-1161, 2007.

3. Fu-Wei Chen and Yi-Yu Liu, "Performance-driven dual-rail routing architecture for structured ASIC design style", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, I. 12, pp. 2046-2050, 2010.

4. Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, and Yi-Yu Liu, "Routability optimization for crossbar-switch structured ASIC design", in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, I. 3, pp. 39:1-39:28, 2013.

5. Ting-Wei Hung, Yen-Hao Chen, and Yi-Yu Liu, "Memory management for dual-addressing memory architecture", in IEICE Electronics Express (ELEX), Vol. 10, I. 15, pp. 1-10, 2013.

6. Po-Yang Hsu, Yung-Chih Chen, and Yi-Yu Liu, "Hybrid LUT and SOP reconfigurable architecture", in Academia Sinica Journal of Information Science and Engineering (JISE), Vol. 30, I. 1, pp. 65-84, 2014.

7. Po-Yang Hsu and Yi-Yu Liu, "Buffer design and assignment algorithm for structured ASIC optimization", in Academia Sinica Journal of Information Science and Engineering (JISE), Vol. 30, I. 1, pp. 107-124, 2014.

8. Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Chung-Hao Wu, and TingTing Hwang, "A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, I. 3, pp. 820-832, 2017.

9. Yi-Yu Liu, "多元入學學生背景差異之課程設計與成效評估：以科大資工系為例", in 教學實踐研究期刊, Vol. 1, I. 1, pp. 105-127.

10. Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, and Tai Chang, "TSE: Two-step elimination for MLC STT-RAM last-level cache", in IEEE Transactions on Computers (TC), Vol. 70, I. 9, pp. 1498-1510, 2021.

11. Jun-Sheng Wu, Chi-An Pan, and Yi-Yu Liu, "ILP-based substrate routing with mismatched via dimension consideration for wire-bonding FBGA package design", in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 28, I. 5, No. 77, pp. 1-26, 2023.

12. Ming-Yen Chuang, Yu-En Lin, and Yi-Yu Liu, "Clustered-based multi-pin substrate routing optimization for fine-pitch ball grid array", accepted and to appear in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. x, I. x, No. xx, pp. 1-24, 2025.

13. Chen-Yu Hsieh, Yu-En Lin, and Yi-Yu Liu, "Optimization heuristics for grid-based integer linear programming package substrate router", accepted and to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. x, I. x, pp. xx-xx, 2025.

Conference papers

1. Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, and Chung-Laung Liu, "Binary decision diagram with minimum expected path length", in Proceedings of ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 708-712, 2001.

2. Yi-Yu Liu, Kuo-Hua Wang, and TingTing Hwang, "Crosstalk minimization in logic synthesis for PLA", in Proceedings of ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 790-795, 2004.

3. Yi-Yu Liu and TingTing Hwang, "Crosstalk-aware domino logic synthesis", in Proceedings of ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 1312-1317, 2006.

4. Fu-Wei Chen and Yi-Yu Liu, "Wire sizing alternative - An uniform dual-rail routing architecture", in Proceedings of ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 796-799, 2008.

5. Fu-Wei Chen and Yi-Yu Liu, "Performance-driven dual-rail insertion for chip-level pre-fabricated design", in Proceedings of ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 308-311, 2009.

6. Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, and Yi-Yu Liu, "Buffer design and optimization for LUT-based structured ASIC design styles", in Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 377-380, 2009.

7. Po-Yang Hsu, Ping-Chuan Lu, and Yi-Yu Liu, "An efficient hybrid LUT/SOP reconfigurable architecture", in Proceedings of IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), pp. 173-176, 2010.

8. Yi-Huang Hung, Hung-Yi Li, Po-Yang Hsu, and Yi-Yu Liu, "Dangling-wire avoidance routing for crossbar switch structured ASIC design style", in Proceedings of IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), pp. 177-180, 2010.

9. Chiu-Yi Chan, Jiun-Li Lin, Lung-Sheng Chien, Tsung-Yi Ho, and Yi-Yu Liu, "GPU-based line probing techniques for Mikami routing algorithm", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 340-344, 2012.

10. Yen-Hao Chen and Yi-Yu Liu, "Dual-addressing memory architecture for two-dimensional memory access patterns", in Proceedings of ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 71-76, 2013.

11. Ting-Wei Hung, Yen-Hao Chen, and Yi-Yu Liu, "Memory management for dual-addressing memory architecture", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 50-55, 2013.

12. Li-Yen Chang, Chen-Hua Suo, and Yi-Yu Liu, "Counter-based victim cache hit rate optimization", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 317-318, 2015.

13. Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C. H. Wu, and TingTing Hwang, "A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements", in Proceedings of ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 79-84, 2016.

14. Shu-Ping Liang and Yi-Yu Liu, "Symmetric segmented delta encoding for wireless sensor data compression", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 4-9, 2016.

15. Chun-Chia Kuo and Yi-Yu Liu, "Voltage-drop aware timing analysis for pessimism design constraint prevention", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 264-265, 2018.

16. Yu-Chun Chou, Pin-Chieh Huang, and Yi-Yu Liu, "Design and evaluation of a bi-directional data acquisition and control system for small-scale solar power plants", in Proceedings of International Conference on Intelligent Green Building and Smart Grid (IGBSG), pp. 339-344, 2019.

17. Jun-Sheng Wu, Chi-An Pan, and Yi-Yu Liu, "Generalized via pattern awareness substrate routing framework for fine pitch ball grid array", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 150-151, 2019.

18. An-Jie Shih, Shao-Yun Fang, and Yi-Yu Liu, "Guiding template design for lamellar DSA with multiple patterning and self-aligned via process", in Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 1-6, 2020.

19. Yu-Sheng Qin, Xiao-Yu Wang, and Yi-Yu Liu, "Power domain layer assignment in package substrate design", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 29-32, 2021.

20. Geng-Shen Lin and Yi-Yu Liu, "Design automation for wire-bond package die orientation and placement", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 120-123, 2021.

21. Yu-En Lin, Che-Hsu Lin, and Yi-Yu Liu, "Wire-bond package finger placement with minimal distance", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 186-191, 2021.

22. Hsiao-Chieh Ma and Yi-Yu Liu, "PCB component copper landing pad design optimization", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 210-215, 2022.

23. Ming-Yen Chuang and Yi-Yu Liu, "Multi-pin net substrate routing framework for fine pitch ball grid array", in Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 62-67, 2024.

24. Yu-En Lin and Yi-Yu Liu, "Wire-bonding finger placement for FBGA substrate layout design with finger orientation consideration", in Proceedings of ACM/IEEE Design, Automation and Test in Europe (DATE), pp. 1-6, 2025.

25. Yu-En Lin, Shao-Yun Fang, and Yi-Yu Liu, "Refinement strategies for any-angle package routing with I/O alignment consideration", accepted and to appear in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. xx-xx, 2025.

The DBLP Computer Science Bibliography