CAD Lab - Honor and Activity

Academic Honor and Activity

Academic Honor
1. 劉一宇, Excellent Presentation Award, International PhD Student Workshop on SOC, 2006.
2. 盧炳全, 96學年度優秀教學助理, 2008.
3. Shu-Ting Lee, "Buffer design for structured ASIC", Student Forum at Asia and South Pacific Design Automation Conference (ASP-DAC), 2009.
4. Chien-Feng Liao, "Cell legalization by density-controlled clustering", Student Forum at Asia and South Pacific Design Automation Conference (ASP-DAC), 2009.
5. 蔡梅香、詹久儀、張至, 教育部『九十七學年度大學校院積體電路電腦輔助設計(CAD)軟體製作競賽』佳作 - Design partitioning for 3D IC, 2009.
6. 孫昱人、林俊利, 教育部『九十八學年度大學校院積體電路電腦輔助設計(CAD)軟體製作競賽』佳作 - Isolation cell insertion for low power design, 2010.
7. 蔡梅香、何慧珊、沈之龢, 教育部『九十八學年度大學校院積體電路電腦輔助設計(CAD)軟體製作競賽』佳作 - Static timing analysis with exception paths, 2010.
8. 林俊利, "以CUDA技術發展合適於VLSI實體設計之演算法", 國科會大專生專題研究計畫, NSC-99-2815-C-155-013-E, 2010.
9. 陳衍昊、許智皓, 教育部『九十九學年度大學校院積體電路電腦輔助設計(CAD)軟體製作競賽』佳作 - Numerical optimization on photo-mask - model-based optical proximity correction, 2011.
10. 吳季恆, "以異質計算環境開發之光罩資料處理平台", 國科會大專生專題研究計畫, NSC-100-2815-C-155-017-E, 2011.
11. Tian-Shiang Lu, Yen-Hao Chen, Ming-Hsuan Tu, ACM-ICPC Asia Taiwan National Contest for Private Universities (NCPU), First Place Award, 2011.
12. 何慧珊, Synopsys summer internship, 2011/07 - 2011/08.
13. Tian-Shiang Lu, Yen-Hao Chen, Ming-Hsuan Tu, ACM-ICPC Asia Taiwan National Contest for Private Universities (NCPU), First Place Award, 2012.
14. 蘇珮涵, "以即時和歷史路況實現行車規劃及時間推估之交通雲服務", 科技部大專生專題研究計畫, MOST-103-2815-C-155-020-E, 2014.
15. 索晨華、洪庭偉、徐瑋均, 『2014助教提升線上學習討論競賽』季軍, 2014.
16. 洪奕文, MediaTek internship, 2014/06-2014/09.
17. 莊博堯, MediaTek internship, 2014/06-2014/09.
18. 索晨華, MediaTek internship, 2014/11-2015/06.
19. 徐瑋均, MediaTek internship, 2014/11-2015/12.
20. 洪奕文, MediaTek internship, 2014/11-2015/12.
21. 劉一宇, 元智大學102學年度教學傑出獎, 2014.
22. 梁書萍, "低功率無線感測器之資料壓縮演算法評估、設計與實作", 科技部大專生專題研究計畫, MOST-104-2815-C-155-034-E, 2015.
23. 徐瑋均, 104學年度優秀教學助理, 2016.
24. 陳世翔, "以區段廣播掃描架構減少測試資料量", 科技部大專生專題研究計畫, MOST-106-2813-C-155-021-E, 2016.
25. 劉慧婷、陳思穎、陳世翔、吳峻陞, 教育部『2017國際積體電路電腦輔助設計軟體製作競賽』特優 - Power distribution network optimization, 2017.
26. 林彥宇, MediaTek internship, 2019/07-2019/08.
27. 林宇恩, 林哲旭, Outstanding Paper Award, SASIMI 2021.
28. 劉一宇, 臺灣科技大學109學年度教學傑出獎, 2021.
29. 馬孝傑, 教育部『2021國際積體電路電腦輔助設計軟體製作競賽』特優 - Component copper configuration design optimization for PCB manufacturing process, 2021.
30. 林宇恩, 林哲旭, 李宇哲, 教育部『2021國際積體電路電腦輔助設計軟體製作競賽』佳作 - Macro legalization, 2021.
31. 馬孝傑, Siemens EDA internship, 2022/07-2022/08.
32. 湯敏摯, ANSYS intership, 2023/07-2023/08.
33. 林士傑, 林楷傑, 張家瑞, 教育部『2023國際積體電路電腦輔助設計軟體製作競賽』優等 - Fixed-outline floorplanning with rectilinear soft blocks, 2023.
34. 陳彥宇, 教育部『2023國際積體電路電腦輔助設計軟體製作競賽』優等 - Lossless data compress for memory hard repair, 2023.
35. 紀宇烜, 教育部『2023國際積體電路電腦輔助設計軟體製作競賽』優等 - Lossless data compress for memory hard repair, 2023.
36. 湯敏摯, ANSYS intership, 2024/07-2024/08.
37. 劉一宇, 臺灣科技大學112學年度教學優良獎, 2024
38. 孫文浩, 王信驊, 潘柏丰, 教育部『2024國際積體電路電腦輔助設計軟體製作競賽』優等 - Automatic analog layout for re-generate SDL & placement migration, 2024.
39. 許桓菘, 吳尚陽, 林書芸, 湯敏摯, 教育部『2024國際積體電路電腦輔助設計軟體製作競賽』佳作 - Power and timing optimization using multibit flip-flop, 2024.
40. 林宇恩, TSMC Ph.D. Scholarship Awardee, 2025.
41. 劉承樸, MediaTek intership, 2025/07-2025/08.
42. 曾韵容, ANSYS intership, 2025/07-2025/08.
43. 湯子賢, 曾韵容, 劉承樸, 吳承諺, 教育部『2025國際積體電路電腦輔助設計軟體製作競賽』優等 - Incremental placement optimization beyond detailed placement: Simultaneous gate sizing, buffering, and cell relocation, 2025.

Activities
1. EDA Forum, Title: Wire sizing alternative: A uniform dual-rail routing architecture, Speaker, 2007/10/20.
2. VLSI/CAD Symposium, Session: Physical Design Automation, Co-chair, 2008/08/06.
3. International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Tutorial Session: Challenges and Potentials in 3D IC Design, Chair, 2009/04/27.
4. EDA Workshop, Session: 頂尖國際研討會論文摘要報告與poster討論, Co-chair, 2009/08/27.
5. International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Session: Physical Design for Emerging Technologies, Chair, 2010/04/29.
6. TMUE-CS Seminar, Title: Computer Aided Design for Structured ASIC, Speaker, 2010/05/19.
7. DAT學程核心課程精進計畫成果推廣發表會, Session: 實體設計自動化, Speaker, 2010/08/10.
8. EDA Workshop, Session: 頂尖國際研討會論文摘要報告, Co-chair, 2010/08/19.
9. KMU Invited Talk, Title: 研究生寶典：我要平安度過研究生生涯, Speaker, 2010/10/26.
10. FJU-EE Seminar, Title: Electronic Design Automation in Nano-scale Era, Speaker, 2010/10/30.
11. 教育部『大學校院積體電路電腦輔助設計軟體製作競賽』, Committee Member, 2007-2011.
12. CYCU-EL Seminar, Title: Electronic Design Automation in Nano-scale Era, Speaker, 2011/03/02.
13. KMU Invited Talk, Title: 教授沒有教的事：研究生的成功生存之道, Speaker, 2011/10/04.
14. EDA Forum, Host, 2011, 2012.
15. FJU-CSIE Seminar, Title: General-purpose GPU Computing for Electronic Design Automation, Speaker, 2012/09/29.
16. CYCU-ICE Seminar, Title: General-purpose GPU Computing for Electronic Design Automation, Speaker, 2012/11/12.
17. FJU-CSIE Short Course, Title: From Chip Multiprocessor to Heterogeneous Computing, Speaker, 2012/12/18.
18. National Computer Symposium - Computer Systems Workshop, Technical Program Committee Member, 2013.
19. International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Session: EDA for Circuit Analysis & Design, Co-chair, 2013/04/23.
20. NTNU-AET Seminar, Title: Dual-addressing Memory Architecture Design for Two-dimensional Memory Access Optimization, Speaker, 2013/06/06.
21. NCUE-EE Seminar, Title: From Chip Multiprocessor to Heterogeneous Computing, Speaker, 2013/06/18.
22. VLSI/CAD Symposium, Poster Session: EDA, Testing, and Power Management, Chair, 2013/08/07.
23. NTUST-CSIE Seminar, Title: Dual-addressing Memory Architecture Design for Two-dimensional Memory Access Optimization, Speaker, 2013/09/30.
24. 南昌大學移地教學, Course: Electronic Design Automation, Lecturer, 2013/10.
25. Intelligent Electronics Summer Camp, Co-host, 2013-2014.
26. CYCU-EL Seminar, Title: Dual-addressing Memory Architecture Design for Two-dimensional Memory Access Optimization, Speaker, 2014/04/16.
27. International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Session: Advances in Circuit Optimization, Co-chair, 2014/04/30.
28. EDA Workshop, Session: 頂尖國際研討會論文摘要報告, Co-chair, 2014/12/06.
29. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Organizing Committee Secretary, 2015.
30. 教育部『ICCAD CADathlon Training』, Co-chair, 2015.
31. PU-CI Seminar, Title: Dual-addressing Memory Architecture Design for Two-dimensional Memory Access Optimization, Speaker, 2015.
32. EDA Workshop, Session: 頂尖國際研討會論文摘要報告, Co-chair, 2015/12/12.
33. Asia and South Pacific Design Automation Conference (ASP-DAC), Technical Program Committee Secretary, 2016.
34. 勞動部勞動力發展署『雙軌訓練旗艦計畫』職類檢核課程規劃小組 ─ IC工程, Committee Member, 2016.
35. VLSI/CAD Symposium, Session: Professor 2.0: 智慧電子領域教授教學之挑戰與策略, Speaker, 2016/08/05.
36. International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Tutorial Session: Flash Memory Design and Management, Chair, 2017/04/24.
37. YZU-CSIE Seminar, Title: Dual-addressing Memory Architecture Design for Two-dimensional Memory Access Optimization, Speaker, 2017/05/05.
38. CYCU-ICE Seminar, Title: Simultaneous Signal I/O Pad and Flip-Chip Bump Placement, Speaker, 2017/05/22.
39. FJU-CSIE Seminar, Title: Simultaneous Signal I/O Pad and Flip-Chip Bump Placement, Speaker, 2017/05/27.
40. YZU-CSIE Seminar, Title: Simultaneous Signal I/O Pad and Flip-Chip Bump Placement, Speaker, 2017/06/02.
41. VLSI/CAD Symposium, Session: Timing/Power/Thermal Optimization and DFM, Co-chair, 2017/08/02.
42. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Organizing Committee Secretary, 2019.
43. YZU-CSE Seminar, Title: Power/Ground Bump Assignment Optimization for Flip-chip Design, Speaker, 2019/06/14.
44. III-SSI Seminar, Title: 太陽光電IEC 61850用戶側閘道器與電網即時資訊匯聚平台技術, Speaker, 2019/10/09.
45. FJU-CSIE Seminar, Title: Power/Ground Bump Assignment Optimization for Flip-chip Design, Speaker, 2019/11/16.
46. Great Lakes Symposium on VLSI (GLSVLSI), Technical Program Committee Member, 2020.
47. International Computer Symposium (ICS), Technical Program Committee Member, 2020.
48. YZU-CSE Seminar, Title: Optimization Strategies for Integer Linear Programming Based Ball Grid Array Substrate Router, Speaker, 2020/01/03.
49. YZU-CSE Seminar, Title: Enabling Domain-Specific Accelerators with RISC-V Instruction Set Architecture, Speaker, 2020/06/19.
50. YZU-CSE Seminar, Title: Wire-bond Package Finger Placement with Minimal Distance, Speaker, 2021/05/21.
51. NTUST-教學拾劍社群研討會分享, Title: 數位教學工具使用經驗分享, Speaker, 2021/07/08.
52. VLSI/CAD Symposium, Session: Optimization Techniques for Advanced Manufacturing and Packaging, Chair, 2021/08/05.
53. FJU-CSIE Seminar, Title: Wire-bond Package Finger Placement with Minimal Distance, Speaker, 2021/10/06.
54. NCNU-CSIE Seminar, Title: Clustered-based Multi-pin Fine Pitch Ball Grid Array Substrate Routing Optimization, Speaker, 2022/04/15.
55. FJU-CSIE Seminar, Title: Clustered-based Multi-pin Fine Pitch Ball Grid Array Substrate Routing Optimization, Speaker, 2022/04/30.
56. Asia and South Pacific Design Automation Conference (ASP-DAC), Organizing Committee Secretary, 2022.
57. YZU-CSE Seminar, Title: Clustered-based Multi-pin Fine Pitch Ball Grid Array Substrate Routing Optimization, Speaker, 2022/10/21.
58. EDA Workshop, Session: The Future of Intelligent Chip Design, Chair, 2022/12/10.
59. NTUST-教學拾劍社群研討會分享, Title: ChatGPT使用經驗分享與討論會, Speaker, 2023/04/23.
60. VLSI/CAD Symposium, Session: Learning Based Frameworks in EDA, Co-chair, 2023/08/02.
61. 桃園市立科學展覽會指導教師研習營, Title: 生活與應用科學科(一)/工程學科(一)/電腦與資訊學科, Speaker, 2023/12/02.
62. EDA Workshop, Session: Intelligent System Design for Heterogeneous Integration, Chair, 2023/12/09.
63. YZU-CSE Seminar, Title: DFM-Compliant Substrate Power Plane Layout Partitioning and Optimization, Speaker, 2024/01/05.
64. FJU-CSIE Seminar, Title: DFM-Compliant Substrate Power Plane Layout Partitioning and Optimization, Speaker, 2024/04/13.
65. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Organizing Committee Secretary, 2024.
66. MOE RISC-V Workshop, Title: 以處理器微架構模擬器強化計算機組織課程教學成效, Speaker, 2024/11/15.
67. CAD Contest at ICCAD, Committee Member, 2012-2024.
68. 桃園市中小學科學展覽會, Jury Committee Member, 2018-2019, 2021, 2023-2024.
69. Taiwan Young-Student Physics Tournament (TYPT), Jury Committee Member, 2018-2019, 2021-2025.
70. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Technical Program Committee Member, 2016, 2018, 2021, 2022, 2024, 2025.
71. VLSI/CAD Symposium, Technical Program Committee Member, 2017-2025.
72. International Conference on Computer-Aided Design (ICCAD), Session: How to Become a Better "Physical Designer": Novel Tweaks on Mapping, Partitioning, and Placement, Co-chair, 2025/10/28.
73. Asia and South Pacific Design Automation Conference (ASP-DAC), Session: Timing Analysis and Timing-Aware Physical Synthesis, Co-chair, 2026/01/20.
74. Asia and South Pacific Design Automation Conference (ASP-DAC), Session: Performance-Driven Floorplanning and Global Placement, Co-chair, 2026/01/21.
75. CAD Contest at ICCAD, Co-chair, 2024-2026.
76. Reviewer: ASP-DAC, DAC, DATE, GLSVLSI, ICCAD, ICS, ISCAS, ISQED, JCIE, JISE, NCS, SASIMI, TCAD, TCAS-I, TODAES, TVLSI, VLSI/CAD Symposium.

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