Posters

Elaheh Sadredini, Reza Rahimi and Kevin Skadron. "A Scalable and Efficient in-Memory Interconnect Architecture for Automata Processing"

Wenjie Xiong and Jakub Szefer. "Covert Channel using Cache LRU States"

Jiwon Choe, Tali Moreshet, Maurice Herlihy and Iris Bahar. "Hybrid Skiplist: Combining the Best of Near-Data-Processing and Lock-Free Algorithms"

Gabriella D'Andrea. "MECO: an innovative run-time manager to evaluate the Dynamic Partial Reconguration protability"

Rui Zhang and Cynthia Sturton. "Transys: Leveraging Common Security Properties Across Hardware Designs"

Atefeh Mehrabi, Aninda Manocha, Benjamin Lee and Daniel Sorin. "Prospector: Synthesizing Efficient Accelerators with Statistical Learning"

Atsuko Shimizu and Dmitry Ponomarev. "Mitigating JOP Attacks by Tracking Dispatcher Gadgets"

Azin Heidarshenas, Serif Yesil, Dimitrios Skarlatos, Sasa Misailovic, Adam Morrison and Josep Torrellas. "Sieve: Speeding-up Iterative Graph Processing on a Shared-Memory Platform with Vertex Pruning"

Vijayalakshmi Saravanan. "A Study on Impact of 3D Stacking on Multi-core processors"

Akshitha Sriraman. "SoftSKU: Optimizing Server Architectures for Microservice Diversity @Scale"

Lia Yeh, Maitreyee Emma Dasgupta and Erick Winston. "Benchmarking ZX-Calculus Circuit Optimization Against Qiskit Transpilation"

Nayana Prasad Nagendra and David August. "Mitigating Instruction Cache Misses Among Datacenter Workloads"

Yannan Wu, Joel Emer and Vivienne Sze. "Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs"

Radha Venkatagiri, Khalique Ahmed, Abdulrahman Mahmoud, Sasa Misailovic, Darko Marinov, Christopher W. Fletcher and Sarita V. Adve. "gem5-Approxilyzer: An Open-Source Tool forApplication-Level Soft Error Analysis"

Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd Austin, "Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn"

Maitreyee Emma Dasgupta, Lia Yeh, Yipeng Huang, Margaret Martonosi and Stephen Lyon. "Statistical Assertions for Debugging in Qiskit"

Call For Posters:

Posters are solicited for research related to any aspect of computer architecture. All researchers in the computer architecture fields are welcome to submit their work for presentation at this workshop. Each poster abstract will be reviewed by members of the community. Posters will not be published and hence can be under submission for other conferences or workshops.

Submission Guidelines:

Each submission should be formatted as an extended abstract, describing the research to be presented in the poster. The length of the extended abstract should be at most TWO single-column pages (formatted into the US letter size of 8.5 x 11 inches with fonts no smaller than 10 point size), including all figures and references. The extended abstract must include the names, affiliations and email addresses of all authors and should be submitted as a single PDF file to EasyChair.

Important Dates:

* Abstract Submission Deadline : August 28, 2019 --- EXTENDED Deadline: September 2, 2019

* Author Notification: September 2, 2019 --- EXTENDED Notification: September 4, 2019

* Workshop Date: October 13, 2019