Designing with Neurons

• PI: Prof. Sarma Vrudhula (Arizona State University)

• Ph.D. Students: Ankit Wagle, Gian Singh, Ayushi Dube (Arizona State University)

• Support: My students and I gratefully acknowledge the American public and the following agencies for their generous support: 

  • National Science Foundation (CCF-07028, IIP-1230401, IIP-1331971), 

  • Science Foundation Arizona SFAz-SBC

  • NSF I/UCRC Center for Embedded Systems. 

Motivation:  At various technology nodes in the evolution of CMOS logic, a power-wall was repeatedly encountered, in which the expected improvement in performance as a result of scaling could not be realized due to the excessive power consumption. At each of those stages, the power challenges were addressed by a combination of (1) technology improvements (2) enhancements to circuit architecture and control strategies, and (3) advanced logic synthesis an physical design tools. Finally the most recent (circa 2006) effort resulted in making a significant paradigm shift in processor design, namely, shifting to multiple cores on a die.  Industry is still aggressively pushing scaling, and this is expected to continue for another 10-15 years. However, its ability to fully and continuously exploit scaling to achieve greater functionality and higher performance has started to become increasingly difficult and very costly. 

If there are to be any further advances in reducing power consumption at the logic and circuit levels, the conventional way of computing logic functions which has been the same for more than 50 years, has to be revisited.  

The focus of line of work is to design alternate ways of computing logic functions, and  develop new circuit architectures that will efficiently perform those logic functions. The purpose is to achieve significant reduction in dynamic and static power consumption without sacrificing (but possibly improving) area and performance. 

Since the threshold function is a Boolean function, it can be realized by a network of conventional logic gates. We do not consider such implementations, and define a threshold logic gate (TLG) as a non-decomposable primitive circuit that computes the weighted sum and evaluates the predicate shown in Equation 1. In the language of neural networks, a TLG is known as a perceptron. 

Why threshold functions? Conventional AND/OR logic primitives are themselves threshold functions, and hence, a network of TLGs may be viewed as a generalization of conventional AND/OR logic networks. However, TLGs are much more powerful than AND/OR gates. For instance, it is well known that to realize a n-bit parity function in two-level sum of products will require an exponential number of gates, whereas a two-level threshold network requires only (n + 1) TLGs. Similarly, multiplication, division, powering, sorting, etc., cannot be computed by a AND/OR circuit of a fixed number of levels and polynomial number of gates, whereas they can be computed by a polynomial size threshold network with a fixed number levels. These are just a smattering of examples that point to the fact threshold networks will have far fewer TLGs, and fewer levels than their counterparts using conventional AND/OR circuits, potentially resulting in significant reductions in power, area and delay, if an efficient, robust implementation of a TLG is possible. 

Looking at the future, the semiconductor industry association (SIA) roadmap predicts further scaling beyond 5nm will not be sustainable, and expects a transition from CMOS to one or more of the presently nascent nano technologies such as resonant tunneling diodes (RTD), carbon nanotube FETs (CNFET) and carbon nanowires; single electron transistors (SET), quantum cellular automata (QCA), non-charge based devices such as spin transfer torque magnetic tunnel junctions (STT-MTJ), and many others. 

An important and distinctive characteristic of these post-CMOS nanotechnologies is that they make it possible to efficiently and naturally implement threshold functions. Threshold functions lie at the heart of neural networks, and neuromorphic computing, and will play a central role in any of the emerging nanotechnologies.  

Presently, we are attempting to develop threshold logic based design for existing CMOS design methodologies, including ASICs and FPGAs,  architectures with memristors, and STT-MTJ devices.   The aim is to see if the theoretical benefits of threshold gates can be realized in conventional CMOS technology.  Our research has demonstrated that this is indeed the case for ASICs.  

Publications (Circuits):

• N. Kulkarni, J. Yang, J.-S. Seo, and S. Vrudhula, “Reducing Power, Leakage and Area of Standard Cell ASICs Using Threshold Logic Flipflops,” IEEE Trans. on VLSI, 2016. Avail. on IEEE Xplore.

• J. Davis, N. Kulkarni, J. Yang, A. Dengi, and S. Vrudhula, “Digital IP Protection Using Threshold Voltage Control,” in Proc. IEEE Symp. Quality Electronic Design (ISQED), Mar. 2016.

• J. Yang, J. Davis, N. Kulkarni, J.-S. Seo, and S. Vrudhula, “Dynamic and Leakage Power Reduction of ASICs Using Configurable Threshold Logic Gates,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), (San Jose, CA), Sept. 2015.

• S. Vrudhula, N. Kulkarni, and J. Yang, “Design of Threshold Logic Gates using Emerging Devices,” in Proceedings IEEE International Symposium on Circuits and Systems, (Lisbon, Portugal), May 2015.

• J. Yang, N. Julkarni, and S. Vrudhula, “Fast and Robust Differential Flipflops and their Extension to Multi-input Threshold Gates,” in Proceedings IEEE International Symposium on Circuits and Systems, (Lisbon, Portugal), pp. 822 – 825, May 2015.

• N. Kulkarni, J. Yang, and S. Vrudhula, “A fast, energy efficient, field programmable threshold- logic array,” in International Conference on Field Programmable Technology, (Shanghai, China), pp. 300 – 305, Dec. 2014.

• Niranjan Kulkarni, Jinghua Yang and Sarma Vrudhula. "A Fast, Energy Efficient, Field Programmable Threshold-Logic Array",  Proc. IEEE Int'l. Conf. on Field Programmable Technology, Shanghai, China, December 2014.

• Jinghua Yang, Niranjan Kulkarni, Shimeng Yu and Sarma Vrudhula. "Integration of Threshold Logic Gate Circuit with RROM Devices for Low Power, and Robust Operation", Proc. EEE/ACM Intenational Symposium on Nanoscale Architectures, Paris, France, July 2014. 

• N. Kulkarni, N. S. Nukala, and S. Vrudhula, “Minimizing area and power of sequential CMOS circuits using threshold decomposition,” in Proc. IEEE Int'l. Conf. on Computer Aided Design (ICCAD), (San Jose, CA), Nov 2012.

• N. S. Nukala, N. Kulkarni, and S. Vrudhula, “Spintronic threshold logic array - a compact, low leakage, non-volatile gate array architecture,” Proc. of the IEEE/ACM Int'l.  Symposium on Nanoscale Architectures, (Amsterdam, Netherlands), July 4-6 2012.

• T. Gowda, S. Vrudhula, N. Kulkarni, and K. Berezowski, “Identification of Threshold Functions and Synthesis of Threshold Networks,” IEEE Trans. on Computer-Aided Design (TCAD), vol. 30, pp. 665–677, May 2011.

• S. Leshner, K. Berezowski, and S. Vrudhula, “Design of a robust, high performance standard cell threshold logic family for deep sub-micron technology,” in Proc. of the IEEE Int'l.  Conf.  on Microelectronics, (Cairo, Egypt), Dec. 19-22 2010.

• S. Leshner, K. Berezowski, X. Yao, G. Chalivendra, S. Patel, and S. Vrudhula, “A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS,” in Proc. of the IEEE Computer Society Annual Symp. on VLSI, (Lixouri Kefalonia, Greece), July 5-7, 2010 2010.

• T. Gowda and S. Vrudhula, “A decomposition based approach for synthesis of multi-level threshold logic circuits,” in Proc. of the Asia and South Pacific Design Automation Conf. , (Seoul, Korea), 21 January 2008.

• T. Gowda, S. Leshner, S. Vrudhula, and G. Konjevod, “Synthesis of threshold logic using tree matching,” in Proc. of the European Conf.  on Circuit Theory and Design (ECCTD), (Sevilla, Spain), 26 August 2007.

• T. Gowda, S. Vrudhula, and G. Konjevod, “A non-ILP based threshold logic synthesis methodology,” in Proc. of the Int'l.  Wkshp on Logic Synthesis (IWLS), (San Diego), 30 May - 1 June 2007. 

Publications (Biology):

• T. Gowda, S. Leshner, S. Vrudhula, and S. Kim, “Threshold logic gene regulatory model: Prediction of dorsal-ventral patterning and hardware based simulation of drosophila,” Proc. of the Int'l. Conf. on Biomedical Electronics and Devices, (Funchal, Madeira, Portugal), 28 January 2008.

• T. Gowda, S. Vrudhula, and S. Kim, “Prediction of pair-wise gene interaction using threshold logic,” Annals of New York Academy of Sciences (NYAS), vol. 1158, no. 1, pp. 276–286, 2009.

• T. Gowda, S. Vrudhula, and S. Kim, “Modeling of gene regulatory network dynamics using threshold logic,” Annals of New York Academy of Sciences (NYAS), vol. 1158, no. 1, pp. 71–81, 2009.

• T. Gowda, S. Leshner, S. Vrudhula, and S. Kim, “Threshold logic gene regulatory networks,” Proc.  IEEE Int'l. Workshop on Genomic Signal Processing and Statistics (GENSIPS), (Tuusula, Finland), 10 June 2007.