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Computer Architecture and the Fetch-Execute Cycle
Computer Architecture and the Fetch-Execute Cycle
Sometimes the behaviour of computers can seem like magic, how do they know how to "run" code? In this topic you'll leverage your logic circuit knowledge to understand how a computer is constructed.
Skills Required in this Topic
Skills Required in this Topic
- Know the components of a von Neumann architecture computer
- Be able to explain the Fetch-Execute cycle used by the CPU
Reminder, a computer is an IPSO device, in this subtopic we'll be focussing on the Processing part.
Details of the types of Input, Output and Storage devices will be left until the hardware part of topic 7.
Components of a Processor
Components of a Processor
The architecture that you need to know for this topic are:
- Memory
- Primary Memory (usually RAM): where both data and programs are stored. (This is for a stored program, von Neumann architecture)
- Cache: Fast memory that stores copies of parts of the RAM that is likely to be used soon.
- L1 cache is built into the CPU
- L2 cache is "nearer" and faster than the main RAM (can be in chip or on motherboard).
- CPU - Central Processing Unit
- Control Unit - Decodes instructions and "controls" the rest of the CPU.
- ALU - Arithmetic Logic Unit - Performs the integer and logic calculations.
- Registers: Fast, small memory in the CPU (also sometimes known as the Immediate Access Store, see BBC Bitesize & 0478_s18_qp_12).
- Program Counter (PC)
- Memory Address Register (MAR)
- Memory Data Register (MDR)
- Current Instruction Register (CIR/IR)
- Accumulator (Acc)
- General Registers (don't use in exams qs)
- Buses - parallel data paths to quickly move data around the computer / motherboard.
- Data Bus
- Address Bus
- Control Bus
Fetch-Decode-Execute Cycle
Fetch-Decode-Execute Cycle
- The address of the next/first instruction is copied from the PC to the MAR
- The Control Bus is set to read and the address reaches the RAM the RAM via the Address Bus. The instruction flows down the Data Bus into the MDR
- The instruction is then copied to the CIR where it is decoded by the Control Unit.
- It is then executed by:
- copying data between the RAM and registers.
- operating on data using the ALU, storing the output in the Accumulator
- branching by updating the PC
- etc...
- The program counter is incremented (can be done any time after step 1).
GCSE CS Guru has the sequence as required in a 2015 Exam - you should have a copy of this in your notes! A 2018 Exam had a slightly different take on the cycle.
von Neumann Computer Architecture
von Neumann Computer Architecture
Requires the I/O, Control Unit, Processor and Primary Memory. This simplified diagram shows some of the details about how they are connected and some of the connections between the registers, CU and ALU inside the CPU.
Note the error in above diagram: Address bus is only unidirectional, not bidirectional!
Possible Extension Topics
Possible Extension Topics
- Floating point units (FPUs) handle the non-integer calculations. Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs) handle even more intensive & parallel floating point calculations.
- Interrupts and Interrupt Registers (Stack)
- Pipelining
- Multicore processors
Board notes from 11SDD 2019...
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