XYScope Dotter Board
What follows below is a brief technical description of Maestro's XYScope "dotter" board. In lab rigs, this device sits in a small enclosure (~12"x10"x5") directly on top of the Maestro PC, with a short high-density ribbon cable (the DSP-Link interface) connecting it to a Spectrum Signal Processing DSP card (either the Detroit C6x or the Dakar F5) installed in the computer. It has outputs to drive the large vector analog oscilloscope -- the so-called XYScope display -- as well as a second smaller scope that serves a monitor by which the researcher can view what stimuli are being presented to the subject during an experiment. The board was designed and constructed in-house by Ken McGary in the now defunct Electronics Shop of UCSF's Department of Physiology. The technical description was copied from the Electronic Shop's old website.
SGL Project 98-1
XY Video Output Board
(Spectrum DSP daughterboard)
KM 8/12/98
Introduction. This circuit board will obtain parallel digital data (16 bits per axis) to provide two high-speed analog outputs driving the X and Y inputs to one of several large-screen XY monitors.
Digital Input Circuitry. The Spectrum DSP-Link interface provides 32 data and 16 address bits, data and address strobes, read/write line, and interrupt lines to connected DSP-Link slave boards. Combinatorial logic provides address decoding and bus direction control, and a small synchronous state machine implemented in D-latches control the pixel timing control.
The Pixel Draw Sequence. The general pixel draw sequence is:
Write Brite-Up Timing Values
Write XY Position Values
Poll Status Bit Until Pixel Draw sequence is Done
IF timing values are the same for next pixel, return to (2) and do it again; ELSE return to (1) and do it again.
Brite-Up Timing. Two registers control the start and end timing of the brite-up pulse. The start value is written to a 4-bit register that sets the time from the XY data write to the beginning of the brite-up pulse. This is to allow for varying settling times on the different monitors, otherwise streaking and other video artifacts may be visible. The start time may be set from .1 to 1.5 us in 100 ns steps (500ns is a typical monitor settling time).
The end time value is stored in an 8-bit register, and controls the time from the XY data write to the end of the brite-up pulse. The brite-up pulse end time may be set to .1 - 25.5 microseconds in .1 m s increments. Both register values are loaded from the dsp-link bus into byte-wide latches previous to any XY data writes, then pre-loaded into down counters at the beginning of each pixel cycle.
Pixel Location Registers. To minimize the time required to write each new pixel, X and Y values are combined into one bus write cycle, thusly:
X video output level - 16 high-order data bits (D31-16).
Y video output level - 16 low-order data bits (D15-0).
The two highest-order address bits (A15-14) act as a "board select" decode. This board’s high-order address is 00.
Register Table.
After the DSTRB signal is received (indicating a stable address and data bus) and assuming a write cycle (R/W_ is low), the data is latched into the two DACs and the pixel write state machine sequence is initiated. As soon as the brite-up pulse is completed, the Pixel Status Bit (PIX_STAT) is cleared, indicating that another Pixel Draw cycle may be started. Two additional timing status bits are included in the status register (END_STAT and START_STAT).
The DSP-Link Standard bus access sequence is used. The DSP-Link bus is asynchronous to this board’s internal 20 MHz clock, so there will be a maximum pixel draw delay of 50 ns after the completion of the bus cycle.
A digital delay line with 25 ns taps (U22) is used to delay the falling edge of DSTRB, ensuring adequate setup and hold times for the data registers. DST_1 provides the clock for signal TIME_CP (U23A), which latches bus data into the Start and Duration Timer registers, and also for DAC_CK (U23B), which latches bus data into the X and Y DAC’s digital inputs. The inverted DAC_CK pulse (CNT_PL) also preloads the start and duration down counters in anticipation of the upcoming Pixel Draw cycle. Both pulses are ended by DST_3, which occurs 50 ns after DST_1.
The counter preload signal (CNT_PL) and starts the Pixel Draw sequence, generating PIX_STAT (U24A) which on the next 10MHz clock edge enables both start and duration counters (START_CE and END_CE). As soon as the preloaded start time has ended, the start timer’s ripple carry output (START_RC) begins the brite-up pulse (U25B, BRITE_UP). The entire Pixel Draw cycle is ended when the duration timer’s ripple carry (END_RC) occurs, clearing all state machine latches and the PIX_STAT status bit, indicating that another cycle may be started.
The DSP-LINK RESET signal will also clear the Pixel Draw state machine, and should be activated before the first cycle is started and on system power-up. An on-board timer (U26) also provide a power-up reset in case the DSP-Link bus is not connected when the board is powered up. This device also includes a watchdog timer which can be retriggered by either the board clock (10MHz) or by each pixel draw cycle (selected by jumper JWD). This watchdog timer prevents monitor phosphor damage if the timing cycle is somehow corrupted.
SCSI-type line termination is provided for all bus control as required by the DSP-LINK interface standard. This termination may be disabled by grounding the JTERM 2-pin header.
Video output circuitry. The only DAC on the market to provide the combination of 16-bit resolution and <200ns settling time is the AD768 from Analog Devices. Therefore, a pair of these IC's form the analog core of this circuit design. This D/A is a current-output device, producing 10mA full-scale for a nominal ladder reference current of 2.5mA (2.5V & 1000W series reference current resistor). A very high speed voltage-feedback op-amp (AD9631) is used as a differential amplifier for the DAC output buffer circuit. This amplifier’s feedback capacitor neutralizes the pole created by the DAC’s output capacitance and the amplifier’s input capacitance, as well as the circuit board trace parasitic capacitance, estimated at about 15 pF. The capacitor value may require adjustment during final circuit evaluation. With the DAC’s 10mA FS output, and a 100W feedback resistor, the buffer output is +/- 1V.
Another gain stage is used to drive the XY monitor’s coaxial cable, resulting in a +/-2.5V video signal. Since proper impedance matching is crucial to maintaining signal fidelity, the coaxial cable is back-terminated with a series 50W resistor, matching the termination at the monitor end of the cable. Note however that this results in a final monitor signal voltage only half that produced by the cable drive amplifier (+/-1.25V).
Circuitry is provided for both single-ended and differential video transmission. For initial system evaluation and debugging, single-ended 50W coax will be used (JPX and JPY). A shielded differential pair (twinax) may be configured by adding the inverting amplifiers’ outputs to a twisted-pair transmission line (JMX and JMY).
Power supply. A distributed power approach is used to reduce analog/digital noise coupling. A triple output (5V, +/-12V) supply is mounted external but immediately adjacent to the circuit board, and connected via heavy-gauge shielded, twisted pair cable. These power rails are then regulated and filtered locally for both analog and digital sections of the board. A split ground and power plane on the circuit board is joined near the power connector and DAC power pins. Ferrite bead/capacitor filters are used between both analog and digital regulator inputs and the power connector. In addition, each IC's power pin is capacitively bypassed to the ground plane, and some high-power high-speed IC's (oscillator, bus drivers, DAC) have additional ferrite power filters.
Power Supply Current Budget.
Analog +5V: DAC *2 = 80 mA; AD9631 * 6 = 25*6= 150 mA.
Analog –5V: DAC*2 = 150 mA; AD9631*6 = 150mA.
Digital +5V: Clock osc – 60mA; 74F74 x 3 = 45mA; 74F gates x 3 = 30 mA.
SCSI terminator: 280 mA
Monitor Interface. Since the three monitors being used all have different input signal requirements, customized interface boxes at each monitor will convert the nominal +/-1.25V video from the DSP-Link output to the specific signal configurations required by each monitor. This will eliminate any chance of miswiring when moving the unit from one monitor to another. The signal requirements for each display are outlined below:
HP Model 1304A X-Y Display
X,Y inputs are differential (separate BNC for +/-), S/B terminated with 50 ohms, +/-2.5V input range FS , 100mV/division.
Z input is differential, 1-2.5V (1= no trace, 2.5 = full brightness).
TTL Blanking input overrides Z input; S/B terminated w/ <200 ohms.
HP Model 1321B X-Y Display
X,Y inputs are differential or single-ended, isolated BNC for each when terminated w/50 ohms, +/-5V input range.
Z input is single ended, BNC; -1V=BLANK, +1V = max bright.
TTL Blanking Input overrides Z input; high = blank.
XYTRON A21-63 Monitor
X,Y inputs are single-ended, BNC for each, 1K input impedence, +/- 5V input range.
Z input is single-ended, BNC;1K input impedence, 0-2.5V input range 0V=blank, 2.5V=max bright.
NO TTL BLANKING!!!