Floating-point & Graphics Unit (FGU)

OpenSPARC T2 has 1 FGU (Floting-point processing Unit) per core. Section 7 of the "OpenSPARC T2 Core Microarchitecture Specification" defines the FGU specification.

The FGU Verilog sources are contained in the following files:

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fac_ctl.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fad_dp.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdc_ctl.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdd_dp.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fec_ctl.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fgd_dp.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fic_ctl.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpc_ctl.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpe_dp.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpf_dp.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpy_dp.v

$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_rep_dp.v

The top level module of FGU is fgu.v .

FGU has three main execution pipelines:

• • Floating-point Execution Pipeline (FPX)

  • Grpahics Execution Pipeline (FGX)

  • Floating-point Divide and square root Pipeline (FDP)

FGU has six stage pipeline, FX1..5 and Fb.