Cache Crossbar (CCX)

The CCX in OpenSPARC is an 8x9 crossbar switch, that acts as a data traffic controller between 8 cores, 8 L2 cache and 1 I/O hub (SIO).

The Verilog RTL source files can be found in sub-dir: $DV_ROOT/design/sys/iop/ccx/rtl

The top level module is ccx.v : $DV_ROOT/design/sys/iop/ccx/rtl/ccx.v

There are 51 additional sub-modules, implementing the design.

CCX design is divided into two parts, PCX pcx.v : $DV_ROOT/design/sys/iop/ccx/rtl/pcx.v and CPX, cpx.v :

$DV_ROOT/design/sys/iop/ccx/rtl/cpx.v

PCX routes data traffic controller from Processor Cores to the crossbar, and CPX regulates the data flow from cache to processor.

The PCX packets are of 130 bits and CPX packets are 146 bit wide.

The CCX is optimized for FPGA synthesis, using ifndef/ifdef FPGA, construct. For example, the spare cells placed in the silicon real estate are removed in the FPGA version to save on the LUT counts.

The crossbar components, PCX and CPX are complementary, that is the design is similar except for they flow the data in opposite directions. Each have 3 stage pipeline : Request (Q), Arbitration (A) and Transmit (X). That is for PCX the three cycles are PQ,PA,PX and for the CPX the cycle (or stages) are called CQ, CA, CX.

Due to arbitration logic and FIFO queue involved the actual data transmission may take many cycles to pass through these three stages.

The arbitration logic, ccx_arb.v , is shared between PCX and CPX, $DV_ROOT/design/sys/iop/ccx/rtl/ccx_arb.v

The Crossbar design is a binary tree of mux see fig 6-1 on pg 129/296 of the "OpenSPARC T2 Core Microarchitecture Specification"