[Citation Statistics from Google Scholar] 

2024

Conference

• [ISCAS'24][Invited to TCAS-II] J. Mu, L. Lu, J. E. Kim, B. An, V. Sharma, A. J. Lekshmi, P. A. Dananjaya, W. H. Lai, W. S. Lew, and T. Kim, "A 1Mb RRAM Macro with 9.8ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation," IEEE International Symposium on Circuits and Systems, May 2024 [Paper]

• [ISCAS'24] Z. Li, W. Lu, Y. Lu, J. Li, Y. Shi, Y. Zheng, and T. Kim, "A Energy-Efficient Object Detection System in IoT with Dynamic Neuromorphic Vision Sensors," IEEE International Symposium on Circuits and Systems, May 2024 [Accepted]

• [ISCAS'24] B. An, X. Zhang, A. T. Do, and T. Kim, "Time-Based Sensing with Linear Current-to-Time Conversion for Multi-Level Resistive Memory," IEEE International Symposium on Circuits and Systems, May 2024 [Accepted]

• [ISCAS'24] Y. Lu, K. Cui, Y. Shi, Z. Li, J. Li, W. Lu, Y. Zheng, and T. Kim, "A Memory-Efficient High-Speed Event-Based Object Tracking System," IEEE International Symposium on Circuits and Systems, May 2024 [Accepted]

• [ISCAS'24] Z, Wei, B. Dong, Y. Su, C. Yang, Y. Lu, T. Kim, and Y. Zheng, "A 2.793µW Near-Threshold Neuronal Population Dynamics Simulator for Reliable Simultaneous Localization and Mapping," IEEE International Symposium on Circuits and Systems, May 2024 [Accepted]

• [ISCAS'24][Demo] Z. Li, W. Lu, Y. Lu, J. Li, Y. Shi, Y. Zheng, and T. Kim, "Live Demonstration: Real-Time Object Detection & Classification System in IoT with Dynamic Neuromorphic Vision Sensors," IEEE International Symposium on Circuits and Systems, May 2024 [Accepted]

• [CICC'24] Z. Li, Y. Lu, A. T. Do, and T. Kim, "A 0.0042nJPixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-path Aggregation Semi-Global Matching," IEEE Custom Integrated Circuits Conference, Apr. 2024 [Accepted]

• [ICEIC'24] K.-C. An, J.-Y. Li, C.-F. Yang, N. Timothy, S. Varku, Q. Wu, P. Kajal, N. Mathews, A. Basu, and T. Kim, "A Dynamic Gesture Recognition Algorithm Using Single Halide Perovskite Photovoltaic Cell for Human-Machine Interaction," The 23rd Intl. Conf. on Electronics, Information, and Communication, Jan. 2024, pp. 1-4, doi: 10.1109/ICEIC61013.2024.10457182. [Paper]

Journal

• [TCAS-I'24] Z. Wei, J. Mu, Z. Lu, Y. Zheng, T. Kim, and B. Kim, "A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing," IEEE Transactions on Circuits and Systems-I [Submitted]

• [TVLSI'24] B. An, X. Zhang, A. T. Do, and T. Kim, "Time-based Sensing with Linear Current-to-Time Conversion for Multi-level Resistive Memory," IEEE Transactions on VLSI Systems [Submitted]

• [JEI'24] W. Lu, Z. Li, J. Li, Y. Lu, and T. Kim, "Event-frame object detection under dynamic background condition," SPIE Journal of Electronic Imaging [Submitted]

• [JSSC'24] Y. Lu, X. Zhang, B. Wang, and T. Kim, "SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor for IoT Devices," IEEE Journal of Solid-State Circuits [Submitted]

• [SSC-L'24] C. Yu, J. Mu, K. Chai, T. Kim, and B. Kim, "A Mixed-Signal Ising Machine Featuring a 48×40 Continuous-Time Inverter Chain Spin Array," IEEE Solid-State Circuits Letters [Submitted]

• [SENSORS'24] K.-C. An, N. Narasimman, and T. Kim, "A High-Resolution Discrete-Time 2nd-order ΣΔ ADC with Improved Tolerance to KT/C Noise using Low Oversampling Ratio," Sensors [in Revision]

• [TCAS-I'24] C. Yu, H. Jiang, J. Mu, K. Chai, T. Kim, and B. Kim, "A Dual 7T SRAM-Based Zero-Skipping Computing-In-Memory Macro with 1-6b Binary Searching ADCs for Processing Quantized Neural Networks," IEEE Transactions on Circuits and Systems-I [in Revision]

• [TCAS-II'24] X. Zhang, Y.-J. Jo, and T. Kim, "A 65nm 55.8TOPS/W Compact 2T DRAM-Based Compute-in-Memory Accelerator with Linear Calibration," IEEE Transactions on Circuits and Systems-II [in Revision]

• [JSTS'24] B.-K. An, X. Zhang, A. T. Do, and T. Kim, "Design of a Reliable Current Sense Amplifier with Dynamic Reference for Resistive Memory," Journal of Semiconductor Technology and Science [Accepted]

• [TCAS-II'24][Invited] J. Mu, L. Lu, J. E. Kim, B. An, V. Sharma, A. J. Lekshmi, P. A. Dananjaya, W. H. Lai, W. S. Lew, and T. Kim, "A 1Mb RRAM Macro with 9.8ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation," IEEE Transactions on Circuits and Systems-II [Paper]

• [TCAS-II'24] D.-H. Shin, C. Jang, Y. Kim, T. Kim, S. Lee, and K.-H. Baek, "An Inductance-Variation-Insensitive Buck Converter using a Dynamic Ramp Compensation with Slope Sensing Technique," IEEE Transactions on Circuits and Systems-II [Paper]

• [JSSC'24] J. Mu, C. Yu, T. Kim, and B. Kim, "A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2D/3D Partial Differential Equations," IEEE Journal of Solid-State Circuits [Paper]

• [TCAS-II'24] C. Jang, D.-H. Shin, Y.-K. Kim, T. Kim, S. Lee, and K.-H. Baek, "A Reconfigurable Step-Down Switched-Capacitor Power Converter Using Optimized Partial Series-Parallel (OPSP) Topology," IEEE Transactions on Circuits and Systems-II [Paper]

• [JSSC'24] Y. Lu, Z. Li, and T. Kim, "HGRP: A 181μW Real-Time Hand Gesture Recognition Processor based on Bi-directional Convolution and Iteration-free Feature Clustering," IEEE Journal of Solid-State Circuits [Paper]

• [JSSC'24] Y. Su, T. Kim, and B. Kim, "FlexSpin: A CMOS Ising Machine with 256 Flexible Spin Processing Elements with 8b Coefficients for Solving Combinatorial Optimization Problems," IEEE Journal of Solid-State Circuits [Paper]

• [JSSC'24] D.-H. Yoon, K.-H. Baek, and T. Kim, "A 2.5 GHz Dynamic Performance-Enhanced Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process," IEEE Journal of Solid-State Circuits [Paper]

• [TCAS-I'24] K.-C. An, N. Narasimman, and T. Kim, "A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣADC Suitable for DVFS," IEEE Transactions on Circuits and Systems-I, vol. 71, pp. 1481-1494, April 2024 [Paper]

2023

Conference

• [A-SSCC'23][Distinguished Design Award][Invited to CICC2024] Y. Lu, X. Zhang, B. Wang, and T. Kim, "SESOMP: A Scalable Energy-Efficient Self-Organizing Map Processor with Compute-In-Memory and Dead Neuron Pruning," IEEE Asian Solid-State Circuits Conference, Nov. 2023, pp. 1-3, doi: 10.1109/A-SSCC58667.2023.10347932. [Paper]

• [A-SSCC'23] X. Zhang, V. Sharma, Y. Lu, Y. Jo, and T. Kim, "A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SAM-Basd Digital Compute-In-Memory Macro for Accelerating CNNs," IEEE Asian Solid-State Circuits Conference, Nov. 2023, pp. 1-3, doi: 10.1109/A-SSCC58667.2023.10347952. [Paper]

• [A-SSCC'23] D.-H. Yoon, J. He, K.-H. Baek, Y. Choi, J.-H. Choi, and T. Kim, "A Time-based PAM-4 Transceiver using Single Path Decoder and Fast-Stochastic Calibration Techniques," IEEE Asian Solid-State Circuits Conference, Nov. 2023, pp. 1-3, doi: 10.1109/A-SSCC58667.2023.10347939. [Paper]

• [SOVC'23] J. Mu, C. Yu, T. Kim, and B. Kim, "A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations," IEEE Symposium on VLSI Circuits, June 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185162 [Paper]

• [NEWCAS'23] B. An, X. Zhang, A. T. Do, and T. Kim, "Design of a Current Sense Amplifier with Dynamic Reference for Reliable Resistive Memory," IEEE Interregional NEWCAS Conference, June 2023, pp. 1-5, doi: 10.1109/NEWCAS57931.2023.10198038 [Paper]

• [ISCAS'23][Invited to TCAS-II] X. Zhang*, Y. Lu*, B. Wang, and T. Kim, "A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration," IEEE International Symposium on Circuits and Systems, May 2023 [Paper] (* equally contributed authors)

• [ISCAS'23] J. He, D.-H. Yoon, and T. Kim, "An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory," IEEE International Symposium on Circuits and Systems, May 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181848 [Paper]

• [ISCAS'23] Z. Wei, J. Mu, Y. Zheng, T. Kim, and B. Kim, "A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing," IEEE International Symposium on Circuits and Systems, May 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181454. [Paper]

• [ISCAS'23] Q. Zang, W. L. Goh, L. Lu, C. Yu, J. Mu, T. Kim, B. Kim, D. Li, and A. T. Do, "282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing," IEEE International Symposium on Circuits and Systems, May 2023,  pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181435 [Paper]

• [CICC'23] Y.-J. Jo, B. P. Yap, D.-H. Yoon, H. Kim, Y. Zheng, and T. Kim, "DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC," IEEE Custom Integrated Circuits Conference, Apr. 2023, pp. 1-2, doi:  10.1109/CICC57935.2023.10121213 [Paper]

• [CICC'23] C. Yu, J. Mu, K. Chai, T. Kim, and B. Kim, "A Continuous-Time Ising Machine Using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates," IEEE Custom Integrated Circuits Conference, Apr. 2023, pp. 1-2, doi: 10.1109/CICC57935.2023.10121286. [Paper]

• [CICC'23][Invited to SSC-L] Y. Su, T. Kim, and B. Kim, "A Reconfigurable Ising Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions," IEEE Custom Integrated Circuits Conference, Apr. 2023, pp. 1-2, doi: 10.1109/CICC57935.2023.10121303  [Paper]

Journal

• [SSC-L'23][Invited] Y. Su, T. Kim, and B. Kim, "A Reconfigurable CMOS Ising Machine with Three-Body Spin Interactions for Solving Boolean Satisfiability with Direct Mapping," IEEE Solid-State Circuits Letters, vol. 6, pp. 221-224, doi: 10.1109/LSSC.2023.3303332  [Paper]

• [JSSC'23] C. Yu, J. Mu, Y. Su, K. Chai, T. Kim, and B. Kim, "A Time-Domain Wavefront Computing Accelerator with a 32×32 Reconfigurable PE Array," IEEE Journal of Solid-State Circuits, vol. 58, pp. 2372-2382, August 2023  [Paper]

• [TCAS-II'23][Invited] X. Zhang*, Y. Lu*, B. Wang, and T. Kim, "A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration," IEEE Transactions on Circuits and Systems-II, vol. 70, pp. 1744-1748, May 2023  [Paper] (* equally contributed authors)

• [TCAS-I'23] Y. Chen, J. Mu, H. Kim, L. Lu, and T. Kim, "BP-SCIM: A Reconfigurable 8T SRAM Macro      for Bit-Parallel Searching and Computing In-Memory," IEEE Transactions on Circuits and Systems-I, vol. 70, pp. 2016-2027, May 2023 [Paper]

• [SSC-L'23] [Invited] J. E. Kim*, D.-H. Yoon*, J. Song, K.-H. Baek, J.-H. Choi, and T. Kim, "A 6 Gbps PAM-3 Transceiver with Background Time-Varying Offset Sensing and Compensation," IEEE Solid-State Circuits Letters, vol. 6, pp. 85-88, 2023 [Paper] (* equally contributed authors)

• [SSC-L'23] [Invited] Y.-J. Jo*, X. Zhang*, J. Liu, J. Zhou, Y. Zheng, and T. Kim, "Transposable 9T-SRAM Computation-In-Memory for On-Chip Learning with Probability-Based Single-Slope SAR Hybrid ADC for Edge Devices," IEEE Solid-State Circuits Letters, vol. 6, pp. 81-84, 2023 [Paper] (* equally contributed authors)

• [TCAS-I'23] H. Kim, J. Mu, C. Yu, T. Kim, and B. Kim, "A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks," IEEE Transactions on Circuits and Systems-I, vol. 70, pp. 1580-1590, Apr. 2023 [Paper]

• [JSSC'23] Y. Lu, V. L. Le, and T. Kim, "A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN," IEEE Journal of Solid-State Circuits, vol. 58, pp. 530-542, Feb. 2023 [Paper]

• [TCAS-I'23] X. Zhang, B. An, and T. Kim, "A Robust Time-based Multi-level Sensing Circuit for Resistive Memory," IEEE Transactions on Circuits and Systems-I, vol. 70, pp. 340-352, Jan. 2023 [Paper]

2022

Conference

• [A-SSCC'22] [Invited to SSC-L] X. Zhang*, Y. Jo*, J. Liu, J. Zhou, Y. Zheng, and T. Kim, "A Local Transpose 9T SRAM Compute-In-Memory Macro with Programmable Single-Slope SAR ADC," IEEE Asian Solid-State Circuits Conference, Nov. 2022, pp. 6-8, doi: 10.1109/A-SSCC56115.2022.9980672 [Paper] (* equally contributed authors)

• [A-SSCC'22] [Invited to SSC-L] J. E. Kim, D.-H. Yoon, J. Song, K.-H. Baek, J.-H. Choi, and T. Kim, "A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation," IEEE Asian Solid-State Circuits Conference, Nov. 2022, pp. 1-3, doi: 10.1109/A-SSCC56115.2022.9980713 [Paper]

• [ISOCC'22][Invited: Special Session] Y. Lu, Z. Li, X. Zhang, and T. Kim, "A Low-Power Gesture Recognition System Utilizing Hybrid Tiny Classifiers," 19th International SoC Design Conference, Oct. 2022, pp. 245-246, doi: 10.1109/ISOCC56007.2022.10031331 [Paper]

• [ESSCIRC'22] D.-H. Yoon, K.-H. Baek, and T. Kim, "A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process," IEEE European Solid-State Circuits Conference, Sept. 2022, pp. 241-244, doi: 10.1109/ESSCIRC55480.2022.9911334 [Paper]

• [ESSCIRC'22] J. Mu, C. Yu, T. Kim, and B. Kim, "A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method," IEEE European Solid-State Circuits Conference, Sept. 2022, pp. 353-356 doi:  10.1109/ESSCIRC55480.2022.9911460 [Paper]

• [AICAS'22][Live Demo] Y. Lu, Z. Li, X. Zhang, and T. Kim, "A 181μW Real-Time 3-D Hand-Gesture Recognition System for Edge Applications," IEEE International Conference on Artificial Intelligence Circuits and Systems, June 2022, pp. 502-502, doi: 10.1109/AICAS54282.2022.9869899  [Paper]

• [ISCAS'22] Y. Chen, J. Mu, H. Kim, L. Lu, and T. Kim, "A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory," IEEE International Symposium on Circuits and Systems, May 2022,  pp. 2556-2560, doi: 10.1109/ISCAS48785.2022.9937509 [Paper]

• [CICC'22] Y. Lu, Z. Li, Y. Chen, and T. Kim, "A 181μW Real-Time 3-D Hand Gesture Recognition System based on Bi-directional Convolution and Computing-Efficient Feature Clustering," IEEE Custom Integrated Circuits Conference, Apr. 2022, pp. 1-2, doi: 10.1109/CICC53496.2022.9772866 [Paper]

• [ISSCC'22][Student Travel Grant Award] Y. Su, T. Kim, and B. Kim, "FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems," IEEE International Solid-State Circuits Conference, Feb. 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731680 [Paper]

Journal

• [JSSC'22] C. Yu, T. Yoo, K. Chai, T. Kim, and B. Kim, "A 65nm 8T SRAM Compute-In-Memory Macro with Column ADCs for Processing Neural Networks," IEEE Journal of Solid-State Circuits, vol 57, pp. 3466-3476, Nov. 2022 [Paper]

• [TCAS-I'22] V. Sharma, H. Kim, and T. Kim, "A 64Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications," IEEE Transactions on Circuits and Systems-I, vol 69, pp.3284-3296, Aug. 2022 [Paper]

• [TVLSI'22] D.-H. Yoon, D.-K. Jung, K. Seong, T.-H. Eom, J.-S. Han, J. E. Kim, T. Kim, and K.-H. Baek, "A 3.2 GHz 178 fsrms Jitter Sub-Sampling PLL/DLL-Based Injection Locked Clock Multiplier," IEEE Transactions on VLSI Systems, vol. 30, pp. 915-925, July 2022  [Paper]

• [JETCAS'22][Guest Editorial] T. Kim, B. Kim, J.-Y. Kim, and J. Kulkarni, "R evolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, pp. 333-337, June 2022 [Paper]

• [JETCAS'22] D. Kim, C. Yu, S. Xie, Y. Chen, J.-Y. Kim, B. Kim, J. Kulkarni, and T. Kim, "An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, pp. 338-353, June 2022 [Paper]

• [JETCAS'22] V. Sharma, J.-E. Kim, L. Lu, and T. Kim, "A Reconfigurable 16Kb AND8T SRAM Macro with Improved Linearity for Multi-bit Compute-In Memory of Artificial Intelligence Edge Devices," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, pp. 522-535, June 2022 [Paper]

• [TCAS-I'22] L. Lu, T. Yoo, and T. Kim, "A 6T SRAM Based Two-Dimensional Configurable Challenge Response PUF for Portable Device System," IEEE Transactions on Circuits and Systems-I, vol. 69, pp. 2542 - 2552, June 2022 [Paper]

• [TCAS-II'22] L. Lu and T. Kim, "A High Reliable SRAM-Based PUF with Enhanced Challenge-Response Space," IEEE Transactions on Circuits and Systems-II, vol. 69, pp. 589-593, Feb. 2022  [Paper]

Book

• J.-Y. Kim, B. Kim, and T. Kim "Processing-in-Memory for AI from Circuits and Systems," Springer [Book]

2021

Conference

• [ISICAS'21] Y.-J. Jo, J. E. Kim, K.-H. Baek, and T. Kim, "A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS," IEEE International Symposium on Integrated Circuits and Systems, Dec. 2021 [Paper]

• [A-SSCC'21] L. Lu and T. Kim, "A Programmable 6T SRAM-Based PUF with Dynamic Stability Data Masking," IEEE Asian Solid-State Circuits Conference, Nov. 2021, pp. 1-3, doi: 10.1109/A-SSCC53895.2021.9634755  [Paper]

• [A-SSCC'21] D.-H. Yoon, D.-K. Jung, K. Seong, T.-H. Eom, J.-S. Han, J. E. Kim, T. Kim, and K.-H. Baek, "A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement," IEEE Asian Solid-State Circuits Conference, Nov. 2021, pp. 1-3, doi: 10.1109/A-SSCC53895.2021.9634762. [Paper]

• [ESSCIRC'21] K. C. An, N. Narasimman, and T. Kim, "A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications," IEEE European Solid-State Circuits Conference, pp. 219-222, Sept. 2021 [Paper]

• [ESSCIRC'21] C. Yu, K. T. C. Chai, T. Kim, and B. Kim, "A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC," IEEE European Solid-State Circuits Conference, pp. 131-134, Sept. 2021 [Paper]

• [AISCAS'21] [Live Demo] Y. Lu, Z. Li, and T. Kim, "An Ultra-Low-Power Real-Time Hand-Gesture Recognition System for Edge Applications," IEEE International Conference on Artificial Intelligence Circuits & Systems, pp.1-1, June 2021 [Paper]

• [ISCAS'21] Y. Chen, L. Lu, Y. Lu, and T. Kim, "A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory," IEEE International Symposium on Circuits and Systems, pp. 1-5, May 2021 [Paper]

• [ISCAS'21] L. Lu, Y. Chen, and T. Kim, "A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme," IEEE International Symposium on Circuits and Systems, pp. 1-5, May 2021 [Paper]

• [ISCAS'21] V. Sharma, J. Kim, Y. Jo, Y. Chen, and T. Kim, "AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing," IEEE International Symposium on Circuits and Systems, pp. 1-5, May 2021 [Paper]

• [ISSCC'21] Y. Lu, V. L. Le, and T. Kim, "A 184μW Real-time Hand Gesture Recognition System with Hybrid Tiny Classifiers for Smart Wearable Devices," IEEE International Solid-State Circuits Conference, pp. 156-157, Feb. 2021 [Paper]

Journal

• [TBCAS'21][Guest Editorial] D. John, T. Kim, and M. L. Johnston, "Guest Editorial Special Issue on Selected Papers From ISCAS 2021," IEEE Transactions on Biomedical Circuits and Systems, vol. 15, pp. 1126-1128, Dec. 2021  [Paper]

• [SENSORS'21] J.-S. Han, T.-H. Eom, S.-W. Choi, K. Seong, D.-H. Yoon, T. Kim, K.-H. Baek, and Yong Shim "A Reference-Sampling based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator," Sensors, 2021, 21(20), 6824 (Impact Factor: 3.031) [Paper]

• [TVLSI'21] M. S. M. Siddiqui*, Z. C. Lee*, and T. Kim, "A 16-kb 9T Ultralow-Voltage SRAM with Column-based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28nm FDSOI," IEEE Transactions on VLSI Systems, vol. 29, pp. 1707-1719, Oct. 2021 (*equally contributed) [Paper]

• [TCAS-II'21] Y.-J. Jo, J. E. Kim, K.-H. Baek, and T. Kim, "A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS," IEEE Transactions on Circuits and Systems-II, vol. 68, pp. 3088-3092, Sept. 2021  [Paper]

• [JSSC'21] H. Kim, T. Yoo, T. Kim, and B. Kim, "Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks," IEEE Journal of Solid-State Circuits, vol. 56, pp. 2221-2233, July 2021 [Paper]

• [SENSORS'21] N. Narasimman, D. Nag, K. C. T. Chuan, and T. Kim, "A Capacitance to Digital Converter using Continuous Time ΔΣ Modulator for Microphone-based Auscultation," IEEE Sensors Journal, vol. 21, pp. 13373-13383, June 2021  [Paper]

• [TCAS-II'21] W.-G. Ho, K.-S. Chong, T. Kim, and B.-H. Gwee, "A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection," IEEE Transactions on Circuits and Systems-II, vol. 68, pp. 2122-2126, June 2021 [Paper]

• [NANO-L'21] J. Yun, Y. Zeng, M. Kim, C. Gao, Y. Kim, L. Lu, T. Kim, W. Zhao, T.-H. Bae, and S. W. Lee, "Tear based aqueous batteries for smart contact lenses enabled by Prussian blue analogue nanocomposites," Nano Letters,  2021 21 (4), 1659-1665  (Impact Factor: 11.238) [Paper]

• [CSSP'21] N. Narasimman and T. Kim, "An Ultra-low Voltage VCO-based ΔΣ Modulator Using Self-Compensated Current Reference for Variation Tolerance," Circuits, Systems and Signal Processing, 40(3), 1089–1110 2021 [Paper]

• [OJCAS'21] Y. Chen, L. Lu, B. Kim, and T. Kim, "A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications," IEEE Open Journal of Circuits and Systems, vol. 2, pp. 210-222, Feb. 2021 [Paper]

• [TCAS-I'21] C. Yu*, T. Yoo*, H. Kim, T. Kim, K. C. T. Chuan, and B. Kim, "A Logic-Compatible eDRAM Compute-In-Memory with Embedded ADCs for Processing Neural Networks," IEEE Transactions on Circuits and Systems-I (*equally contributed), vol. 68, pp. 667-679, Feb. 2021 [Paper]

Book Chapter

• T. Kim "Circuit Design for Non-volatile Magnetic Memory," in Emerging Non-volatile Memory Technologies: Physics, Engineering, and Applications, Springer [Book]

2020

Conference

• [APCCAS'20] L. Lu, J. E. Kim, V. Sharma, and T. Kim, "ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology," 16th IEEE Asia Pacific Conference on Circuits and Systems, pp. 213-216, Dec. 2020 [Paper] 

• [ISOCC'20][Invited: Special Session] V. L. Le, T. Yoo, J. E. Kim, K.-H. Baek, and T. Kim, "A Low-Power Smart Gesture Sensing SoC with On-chip Image Sensor for Smart Devices," 17th International SoC Design Conference, pp. 171-172, Oct. 2020 [Paper]

• [ISOCC'20][Invited: Special Session] C. Yu, T. Yoo, T. Kim, K. Chai, and B. Kim, "Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks," 17th International SoC Design Conference, pp. 175-176 Oct. 2020 [Paper]

• [ISCAS'20] Y. Chen, L. Lu, B. Kim, and T. Kim, "Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing," IEEE International Symposium on Circuits and Systems, pp. 1-5, October 2020 [Paper]

• [ISCAS'20] A. T. Do, T. Kim, and J. Zhou, "Design and Characterization of Radiation-Hardened MCU for Space Application Using Error Correction SRAM and Glitch Removal Clock Buffer Cell," IEEE International Symposium on Circuits and Systems, pp. 1-4, October 2020 [Paper]

• [ISCAS'20] W.-G. Ho, K.-S. Chong, T Kim, B.-H. Gwee, "A Secure Data-Toggling SRAM for Confidential Data Protection," IEEE International Symposium on Circuits and Systems, pp. 1-1, October 2020 [Paper]

• [CICC'20] C. Yu*, T. Yoo*, T. Kim, K. Chai, and B. Kim, "A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC," IEEE Custom Integrated Circuits Conference, pp. 1-4, Mar. 2020 (*equally contributed) [Paper]

• [DATE'20] Q. Chen, Y. Su, H. Kim, T. Yoo, T. Kim and B. Kim, "A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length," Design, Automation and Test in Europe Conference, pp. 678-681, Mar. 2020 [Paper]

Journal

• [TVLSI'20] Y. Chen, L. Lu, B. Kim, and T. Kim, "Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory," IEEE Transactions on VLSI Systems, Vol. 28, pp. 2636-2649, December 2020 [Paper]

• [TCAS-II'20] A. Do*, S. M. A. Zeinolabedin*, and T. Kim, "Energy-Efficient Data-Aware SRAM Design Utilizing Column-based Data Encoding," IEEE Transactions on Circuits and Systems-II, Vol. 67, pp. 2154 - 2158, October 2020 (*equally contributed) [Paper]

• [TBME'20] S. Liu, W. Song, X. Liao, T. Kim, and Y. Zheng, "Development of a handheld volumetric photoacoustic imaging system with a central-holed 2D matrix aperture," IEEE Transactions on Biomedical Engineering, Vol. 67, pp. 2482-2489, September 2020 [Paper]

• [TVLSI'20] V. L. Le*, T. Yoo*, J. E. Kim, N. Le Ba, K.-H. Baek, and T. Kim, "A 137-µW 1.78-mm2 30-frames/s Real-Time Gesture Recognition SoC for Smart Devices," IEEE Transactions on VLSI Systems, Vol. 28, pp. 1909-1919, August 2020 (*equally contributed) [Paper]

• [NANOEN'20] K. Rawy, R. Sharma, H.-J. Yoon, U. Khan, S.-W. Kim, and T. Kim, "A triboelectric nanogenerator energy harvesting system based on load-aware control for input power from 2.4 μW to 15.6 μW," Nano Energy, Vol.74, August 2020, 104839 (Impact Factor: 15.548) [Paper]

• [TDMR'20] S. M. Siddiqui, S. Ruchi, V. L. Le, T. Yoo, I.-J. Chang,  and T. Kim, "SRAM Radiation Hardening through Self-Refresh Operation and Error Correction," IEEE Transactions on Device and Materials Reliability, Vol. 20, pp. 468-474, June 2020 [Paper]

• [TVLSI'20] L. Lu, T. Yoo, V. L. Le  and T. Kim, "A 0.506-pJ 16-kb 8T SRAM with Vertical Read Word-Lines and Selective Dual Split Power Lines," IEEE Transactions on VLSI Systems, Vol. 28, pp. 1345-1356, June 2020 [Paper]

• [ACCESS'20] J. E. Kim, T. Yoo, D.-K. Jung, D.-H. Yoon, K. Seong, T. Kim, and K.-H. Baek, "A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations," IEEE Access, Vol. 8, pp. 101359-101368 2020 [Paper]

• [SENSORS'20] K. Seong, D.-K. Jung, D.-H. Yoon, J.-S. Han, J.-E. Kim, T. Kim, W. Lee, and K.-H. Baek "Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems," Sensors 2020, 20, 2430 (Impact Factor: 3.031) [Paper] 

2019

Conference

• [BioCAS'19] S. Liu, K. Tang, H. Jin, R. Zhang, T. Kim and Y. Zheng, "Continuous wave laser excitation based portable optoacoustic imaging system for melanoma detection," IEEE Biomedical Circuits and Systems Conference, pp. 1-4, Oct. 2019 [Paper]

• [ISOCC'19] [Invited] T. Kim, "Overview of Memory Design for Next Generation Applications," 16th International SoC Design Conference, pp. 162-163, Oct. 2019 [Paper]

• [ISOCC'19] [Invited] H. Kim, Q. Chen, T. Yoo, T. Kim and B. Kim, “A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks," 16th International SoC Design Conference, pp. 166-167, Oct. 2019 [Paper]

• [ISOCC'19] [Invited] J.-Y. Kweon, Y.-H. Song, and T. Kim, “Modelling of Phase Change Memory (PCM) Cell for Circuit Simulation," 16th International SoC Design Conference, pp. 170-171, Oct. 2019 [Paper]

• [ESSCIRC'19] [Invited to LSSC] V. L. Le, T. Yoo, J. E. Kim, K.-H. Baek, and T. Kim, “A 213.7-μW Gesture Sensing System-on-Chip with Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65-nm”, IEEE European Solid-State Circuits Conference, pp. 123-126, Sept. 2019 [Paper]

• [ESSCIRC'19] H. Kim, Q. Chen, T. Yoo, T. Kim, and B. Kim, “A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation”, IEEE European Solid-State Circuits Conference, pp. 345-348, Sept. 2019 [Paper]

• [ISLPED'19] T. Yoo, H. Kim, Q. Chen, T. Kim, and B. Kim, “A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks”, ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 1-6, July 2019 [Paper]

• [ISCAS'19] L. Lu, and T. Kim, "A Sequence-Dependent Configurable SRAM PUF for Enhanced Challenge Response Space," IEEE International Symposium on Circuits and Systems, pp. 1-5, May 2019 [Paper]

• [EDTM'19] J.-T. Choi, B.-K. An, T. Kim, and Y.-H. Song, "Development of PCM and OTS Macro-models for HSPICE Simulation," 3rd Electron Devices Technology and Manufacturing Conference, pp. 463-465, Mar. 2019 [Paper]

• [ICEIC'19] J.-T. Choi, Y.-H. Song, and T. Kim, "Novel Current-mirror Based Time Dependent Sense Scheme for MLC PRAM," International Conference on Electronics, Information, and Communication, pp. 1-3, Jan. 2019 [Paper]

Journal

• [ELL'19] J. E. Kim, T. Yoo, K.-H. Baek, and T. Kim, "A balanced sampling switch for high linearity and a wide temperature range in low power SAR ADCs," IET Electronics Letters, Vol. 55, Issue 24, pp. 1273-1275 Nov. 2019 [Paper]

• [TCAS-I'19] W.-G. Ho, K.-S. Chong, T. Kim, and B.-H. Gwee, "A Secure Data-Toggling SRAM for Confidential Data Protection," IEEE Transactions on Circuits and Systems-I, Vol. 66, pp. 4189-4199, Nov. 2019 [Paper]

• [LSSC'19] [Invited] V. L. Le, T. Yoo, J. E. Kim, K.-H. Baek, and T. Kim, “A 213.7-μW Gesture Sensing System-on-Chip with Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65-nm”, IEEE Solid-State Circuits Letters, Vol. 2, pp. 123-126, Sept. 2019 [Paper]

• [MEJ'19] A. Garg, Z. C. Lee, L. Lu, and T. Kim, "Improving Uniformity and Reliability of SRAM PUFs Utilizing Device Aging Phenomenon for Unique Identifier Generation," Microelectronics Journal, Elsevier, Vol. 90, pp. 29-38, Aug. 2019 [Paper]

• [JSSC'19] Z. C. Lee*, M. S. M. Siddiqui*, Z. H. Kong, and T. Kim, "An 8T SRAM with On-Chip Dynamic Reliability Management and Two-phase Write Operation in 28-nm FDSOI," IEEE Journal of Solid-State Circuits, Vol. 54, pp. 2091-2101, July 2019 (*equally contributed) [Paper]

• [MEJ'19] N. Le Ba, S. Oh, D. Sylvester, and T. Kim, "A 256 pixel, 21.6 μW Infrared Gesture Recognition Processor for Smart Devices," Microelectronics Journal, Elsevier, Vol. 86, pp. 49-56, Apr. 2019 [Paper]

• [JLPEA'19] M. Jayakrishnan, A. Chang, and T. Kim, "Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience," Journal of Low Power Electronics and Applications, 9, no. 1: 5 [Paper]

• [TVLSI'19] A. Do*, S. M. A. Zeinolabedin*, D. Jeon, D. Sylvester, and T. Kim, "An Area Efficient 128-Channel Spike Sorting Processor for Real-time Neural Recording with 0.175 µW per Channel in 65-nm CMOS," IEEE Transactions on VLSI Systems, (*equally contributed), Vol. 27, pp. 126-137, Jan. 2019 [Paper] 

2018

Conference

• [ISOCC'18] S. M. Siddiqui, R. Sharma, V. L. Le, T. Yoo, I.-J. Chang,  and T. Kim, "A Radiation Hardened SRAM with Self-refresh and Compact Error Correction," 15th International SoC Design Conference, pp. 235-236, Nov. 2018 [Paper]

• [ISOCC'18] K. Lim, M. Choi, M.-T.-L. Aung, K. Kim, J.-Seong Kim, R.-H. Baek, H.-J. Song, T. Kim, and B. Kim, "Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects," 15th International SoC Design Conference, pp. 239-240, Nov. 2018 [Paper]

• [ISOCC'18] D. V. Thai, B.-Y. Jung, K.-H. Baek, T. Yoo, and T. Kim, "A 12-bit 200-MS/s Pipelined ADC using Maximization of Settling Time Scheme," 15th International SoC Design Conference, pp. 97-98, Nov. 2018 [Paper]

• [ISOCC'18] J. Y. Kweon, J. T. Choi, Y.-H. Song  and T. Kim, "Leakage Control System Using Data Estimation of Resistive Memory," 15th International SoC Design Conference, pp. 96-97, Nov. 2018 [Paper]

• [A-SSCC'18] K. Rawy, R. Sharma, H.-J. Yoo, U. Khan, S.-W. Kim, and T. Kim, "An 88% Efficiency 2.4µW to 15.6µW Triboelectric Nanogenerator Energy Harvesting System Based on a Single-Comparator Control Algorithm," IEEE Asian Solid-State Circuits Conference, pp. 33-36, Nov. 2018 [Paper]

• [A-SSCC'18] [Invited to JSSC] L. Lu, T. Yoo, V. L. Le  and T. Kim, "An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write Assist," IEEE Asian Solid-State Circuits Conference, pp. 143-144, Nov. 2018 [Paper]

• [A-SSCC'18] T. Yoo*, V. L. Le*, J. E. Kim, N. L. Ba, K.-H. Baek and T. Kim, "A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices," IEEE Asian Solid-State Circuits Conference, pp. 277-280, Nov. 2018 (*equally contributed) [Paper]

• [ISICAS'18] D.-K. Jung, Y.-H. Jung, T. Yoo, D.-H. Yoon, B.-Y. Jung, T. Kim, and K.-H. Baek, "A 12-bit Multi-Channel R-R DAC using a Shared Resistor String Scheme for Area-Efficient Display Source Driver," International Symposium on Integrated Circuits and Systems, Sept. 2018

• [ISCAS'18] [Invited to TCAS-II] V.-L. Le and T. Kim, "An Area and Energy Efficient Ultra-Low Voltage Level Shifter with Reduced-Swing Output Buffer," IEEE International Symposium on Circuits and Systems, May 2018

• [ICEIC'18] T. Yoo, Y. Choi, D.-H. Yoon, J.-S. Lee, T. Kim, and K.-H. Baek, "A 10Gbps 2-tap pre-emphasis technique for current-mode logic driver in 55nm CMOS," International Conference on Electronics, Information, and Communication, Jan. 2018

Journal

• [TCAS-I'18] D.-K. Jung, Y.-H. Jung, T. Yoo, D.-H. Yoon, B.-Y. Jung, T. Kim, and K.-H. Baek, "A 12-bit Multi-Channel R-R DAC using a Shared Resistor String Scheme for Area-Efficient Display Source Driver," IEEE Transactions on Circuits and Systems-I, Vol. 65, pp. 3688-3697, Nov. 2018 [Paper]

• [TPEL'18] N.-S. Pham, T. Yoo, T. Kim, C.-G. Lee, K.-H. Baek, "A 0.016mV/mA Cross-regulation 5-Output SIMO DC-DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme," IEEE Transactions on Power Electronics, Vol. 33, pp. 9619-9630, Nov. 2018 [Paper]

• [JSSC'18] [Invited] K. Rawy, T. Yoo and T. Kim, "An 88% Efficiency 0.1-300-µW Energy Harvesting System with 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes," IEEE Journal of Solid-State Circuits, Vol. 53, pp. 2751-2762, Oct. 2018 [Paper]

• [JSSC'18] [Invited] V. L. Le, J. Lee, A. Chang and T. Kim, "A 0.4-V 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop with Change-Sensing Scheme in 40-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 53, pp. 2806-2817, Oct. 2018 [Paper]

• [TCAS-I'18] N. L. Ba and T. Kim, "An Area Efficient 1024-point Low Power Radix-22 FFT Processor with Feed-fordward Multiple Delay Commutators," IEEE Transactions on Circuits and Systems-I, Vol. 65, pp. 3291-3299, Oct. 2018 [Paper]

• [TCAS-II'18] [Invited] V.-L. Le and T. Kim, "An Area and Energy Efficient Ultra-Low Voltage Level Shifter with Pass Transistor and Reduced-Swing Output Buffer in 65-nm CMOS," IEEE Transactions on Circuits and Systems-II, Vol. 65, pp. 607-611, May 2018 [Paper]

• [JLPEA'18] M. Jayakrishnan, A. Chang, and T. Kim, "Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications," Journal of Low Power Electronics and Applications, 8, no. 2: 9.  [Paper]

• [SSE'18] T. Kim, Z. Lee, and A. Do, "A 32kb 9T Near-threshold SRAM with Enhanced Read Ability at Ultra-low Voltage Operation," Solid-State Electronics, Vol. 139, pp. 60-68, Jan. 2018 [Paper] 

2017

Conference

• [ISOCC'17] [Invited] T. Yoo, J. Kim, K. Baek and T. Kim, "A 0.5 V CMOS Image Sensor with Adaptive Dynamic Range," 14th International SoC Design Conference, Nov. 2017

• [A-SSCC'17] [Invited to JSSC] V.-L. Le, J. Lee, A. Chang and T. Kim, "A 82% Energy-Saving Change-Sensing Flip-Flop in 40nm CMOS for Ultra-Low Power Applications," IEEE Asian Solid-State Circuits Conference, pp. 197-200, Nov. 2017 [Paper]

• [A-SSCC'17] [Invited to JSSC], [Invited to Student Design Contest] K. Rawy, T. Yoo and T. Kim, "An 88% Efficiency MPPT for PV Energy Harvesting System with Novel Switch Width Modulation for Output Power 100nW to 0.3mW," IEEE Asian Solid-State Circuits Conference, pp. 117-120, Nov. 2017      (A-SSCC 2017 Student Travel Grant Award) [Paper]

• [A-SSCC'17] M. S. M. Siddiqui*, Z. C. Lee*, and T. Kim, "A 16kb Column-Based Split Cell-VSS, Data-Aware Write-Assisted 9T Ultra-Low Voltage SRAM with Enhanced Read Sensing Margin in 28nm FDSOI," IEEE Asian Solid-State Circuits Conference, pp. 165-168, Nov. 2017 (*equally contributed) [Paper]

• [ASICON'17] [Invited] J. Zhou, T. Kim and Y. Lian, "Near-threshold Processor Design Techniques for power-constrained computing devices," 12th International Conference on ASIC, pp. 920-923, Oct. 2017 [Paper]

• [VLSI-SoC'17] M. Jayakrishnan, A. Chang, and T. Kim, "Library Pruning and Sigma Corner Libraries for Power Efficient Variation Tolerant Processor Pipelines," IFIP/IEEE International Conference on Very Large Scale Integration, pp. 1-6, Oct. 2017 [Paper]

• [CICC'17] N. Narasimman, D. Nag, K. C. T. Chuan, and T. Kim, "A 1.2 V, 0.84 pJ/Conv.-Step Ultra-low Power Capacitance to Digital Converter for Microphone based Auscultation," IEEE Custom Integrated Circuits Conference, pp. 1-4, (DOI: 10.1109/CICC.2017.7993661) May 2017 [Paper]

Journal

• [JoS'17] J. Zhou, X. Huang, C. Wang, T. Kim and L. Yong, "Energy Efficient Digital and Wireless IC Design for Wireless Smart Sensing," Journal of Semiconductors, Vol. 38, pp. 105005-1-9, Oct. 2017 [Paper]

• [MEJ'17] B. Wang, J. Zhou, and T. Kim, "A 0.4 V 12T 2RW Dual-Port SRAM with Suppressed Common-Row-Access Disturbance," Microelectronics Journal, Vol. 69, pp. 78-85, Nov. 2017 [Paper]

• [TCAS-I'17] K. Rawy, F. Kalathiparambil, D. Maurath, and T. Kim, "A Self-adaptive Time-Based MPPT with 96.2% Tracking Efficiency and a Wide Tracking Range of 10-µA to 1-mA for IoT Applications," IEEE Transactions on Circuits and Systems-I, Vol. 64, pp. 2334-2345, Sept. 2017  [Paper]     (Special Issue on Circuits and Systems for the Internet of Things—From Sensing to Sensemaking)

• [TVLSI'17] N. L. Ba and T. Kim, "Design of Temperature-Aware Low Voltage 8T SRAM in SOI Technology for High Temperature Operation (25 ~ 300 °C)," IEEE Transactions on VLSI Systems, Vol. 25, pp. 2383-2387, Aug. 2017 [Paper]

• [TVLSI'17] M. Aung, T. Yoshikawa, C. Tan, and T. Kim, "Yield Enhancement of Face-to-Face Cu-Cu Bonding with Dual-mode Transceivers in 3DICs," IEEE Transactions on VLSI Systems, Vol. 25, pp. 1023-1031, Mar. 2017 [Paper] 

• [TCAS-I'17] A. Das, Y. Gao, and T. Kim, "A 220 mV Power-on-Reset Based Self-Starter with 2 nW Quiescent Power for Thermo-electric Energy Harvesting Systems," IEEE Transactions on Circuits and Systems-I, Vol. 64, pp. 217-226, Jan. 2017 [Paper] 

2016

Conference

• [A-SSCC'16] [Invited to Student Design Contest] A. T. Do, S. M. A. Zeinolabedin and T. Kim, "A 0.3 pW/Access 8T Data-Aware SRAM Utilizing Column-based Data Encoding for Ultra-Low Power Applications," IEEE Asian Solid-State Circuits Conference, pp. 173-176, Nov. 2016 [Paper]

• [A-SSCC'16] A. Das, Y. Gao and T. Kim, "An Isolated PoR Based Pulse Generator for TEG Energy Harvesting with Minimum Startup of 150 mV and Maximum Series Resistance of 600 Ω," IEEE Asian Solid-State Circuits Conference, pp. 297-300, Nov. 2016 [Paper]

• [APCCAS'16] M. Aung and T. Kim, "Self-Contained Built-In-Self-Test/Repair Transceivers for Interconnects in 3DICs," IEEE Asia Pacific Conference on Circuits and Systems, pp. 640-641, Oct. 2016 [Paper]

• [APCCAS'16] K. G. Jayaraman, K. Rawy, and T. Kim, "A 0.6-V Power Efficient Digital LDO with 99.7% Current Efficiency Utilizing Load Current Aware Clock Modulation for Fast Transient Response," IEEE Asia Pacific Conference on Circuits and Systems, pp. 103-106, Oct. 2016 [Paper]

• [ICCE-Asia'16] [Invited] T. Kim, D. Trang, and I. Chang, "Design of Energy Efficient Ultra-low Voltage SRAMs for Internet-of-Things Applications," IEEE International Conference on Consumer Electronics Asia, Oct. 2016

• [VLSI-SoC'16] M. Jayakrishnan, A. Chang, and T. Kim, "Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience," IFIP/IEEE International Conference on Very Large Scale Integration, pp. 1-6, Oct. 2016 [Paper]

• [ESSCIRC'16] N. Narasimman and T. Kim, "A 0.3 V, 49 fJ/Conv.-step VCO-based Delta Sigma Modulator with Self-compensated Current Reference for Variation Tolerance," IEEE European Solid-State Circuits Conference, pp. 237-240, Sept. 2016 [Paper]

• [ESSCIRC'16] Z. C. Lee*, M. S. M. Siddiqui*, Z. H. Kong, and T. Kim, "An 8T SRAM with BTI-Aware Stability Monitor and Two-Phase Write Operation for Cell Stability Improvement in 28-nm FDSOI," IEEE European Solid-State Circuits Conference, pp. 437-440, Sept. 2016 (*equally contributed) [Paper]

• [ESSCIRC'16] K. Rawy, F. K. George, D. Maurath, and T. Kim, "A 96.2% Efficiency Time-based Energy-Harvesting MPPT with 5.1µW Power Consumption and 10-µA to 1-mA Tracking Range," IEEE European Solid-State Circuits Conference, pp. 503-506, Sept. 2016 [Paper]

• [SOVC'16] [Low Power Design Contest Award at ISLPED] S. M. A. Zeinolabedin*, A. T. Do*, D. Jeon, D. Sylvester, and T. Kim, "A 128-Channel Spike Sorting Processor Featuring 0.175 µW and 0.0033 mm2 per Channel in 65-nm CMOS," IEEE Symposium on VLSI Circuits, pp. 32-33, June 2016 (*equally contributed) [Paper]

• [SOVC'16] S. Oh, N. L. Ba, S. Bang, J. Jeong, D. Blaauw, T. Kim, and D. Sylvester, "A 260µW Infrared Gesture Recognition System-on-Chip for Smart Devices," IEEE Symposium on VLSI Circuits, pp. 228-229, June 2016 [Paper]

• [ISCAS'16] N. Narasimman and T. Kim, "An Ultra-Low Voltage, VCO-Based ADC with Digital Background Calibration," IEEE International Symposium on Circuits and Systems, pp. 1458-1461, May 2016 [Paper]

• [ISCAS'16] W.-G. Ho, N. P. Srinivas, K.-S. Chong, T. Kim, and B.-H. Gwee, "Area-Efficient and Power-Saving 1K-Byte Transmission-Gated Non-Imprinting High-Speed Erase (TNIHE) SRAM," IEEE International Symposium on Circuits and Systems, pp. 698-701, May 2016 [Paper]

Journal

• [TCAS-I'16] S. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "A Power and Area Efficient Ultra-low Voltage Laplacian Pyramid Processing Engine with Adaptive Data Compression," IEEE Transactions on Circuits and Systems-I , Vol. 63, pp. 1690-1700, Oct. 2016 [Paper]

• [TVLSI'16] M. Aung, T. Lim, T. Yoshikawa, and T. Kim, "2.31 Gbps/ch Area Efficient Crosstalk Cancelled Hybrid Capacitive Coupling Interconnect for 3D Integration," IEEE Transactions on VLSI Systems, Vol. 24, pp. 2703-2711, Aug. 2016 [Paper]

• [JSSC'16] A. Do, Z. Lee, B. Wang, I. Chang, and T. Kim, "0.2 V 8T SRAM with PVT-Aware Bit-line Sensing and Column-based Data Randomization," IEEE Journal of Solid-State Circuits, Vol. 51, pp. 1487-1498, June 2016 [Paper]

• [TVLSI'16] B. Wang, Q. Li, and T. Kim, "Read Bitline Sensing and Fast Local Write-back Techniques in Hierarchical Bitline Architecture for Ultra-low Voltage SRAMs," IEEE Transactions on VLSI Systems, Vol 24, pp. 2165-2173, June 2016 [Paper]

Book Chapter

• T. Kim and A. M. Thu Linn, "Design of High-Speed Interconnects for 3D/2.5D ICs without TSVs," in Physical Design for 3D Integrated Circuits, CRC Press [Book]

2015

Conference

• [ISOCC'15] [Invited] T. Kim and M. Aung, "Capacitive Coupled Contactless Interconnect Design for 3D ICs," 12th International SoC Design Conference, pp. 121-122, Nov. 2015 [Paper]

• [ASICON'15] [Invited] T. Kim and J. Zhou, "Opportunities and Challenges: Ultra-Low Voltage Digital IC Design Techniques," 11th International Conference on ASIC, Nov. 2015 [Paper]

• [VLSI-SoC'15] M. Jayakrishnan, J. P. D. Gyvez, A. Chang, and T. Kim, "Slack-aware Timing Margin Redistribution Technique Utilizing Error Avoidance Flip-Flops and Time Borrowing," IFIP/IEEE International Conference on Very Large Scale Integration, pp. 159-164, Oct. 2015 [Paper]

• [ESSCIRC'15] S. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "A 0.5V Power and Area Efficient Laplacian Pyramid Processing Engine using FIFO with Adaptive Data Compression," IEEE European Solid-State Circuits Conference, pp. 104-107, Sept. 2015 [Paper]

• [ESSCIRC'15] A. Das, Y. Gao, and T. Kim, "A 76% Efficiency Boost Converter with 220mV Self-Startup and 2nW Quiescent Power for High Resistance Thermo-Electric Energy Harvesting," IEEE European Solid-State Circuits Conference, pp. 237-240, Sept. 2015 [Paper]

• [EDSSC'15] [Invited] M. Aung, T. Lim, T. Yoshikawa, and T. Kim, "Design Review on Capacitive Coupling Interconnect for 3DIC," IEEE Conference on Electron Devices and Solid-State Circuits, pp. 245-248, June 2015 [Paper]

• [EDSSC'15] [Invited] C. Wang, J. Zhou, K. Guruprasad, X. Liu, R. Weerasekera, and T. Kim, "TSV-Based PUF Circuit for 3DIC Sensor Nodes in IoT Applications," IEEE Conference on Electron Devices and Solid-State Circuits, pp. 313-316, June 2015 [Paper]

• [EDSSC'15] J. Teh, A. Do, T. Kim, and S. Liter, "A 28.4 pJ per Conversion ISFET-based pH Sensing Design for Low-Energy Applications," IEEE Conference on Electron Devices and Solid-State Circuits, pp. 174-177, June 2015

• [ISCAS'15] [Invited to TCAS-I] A. Do, Z. K.-S. Yeo, and T. Kim, "A 32kb 9T SRAM with PVT-tracking Read Margin Enhancement for Ultra-low Voltage Operation," IEEE International Symposium on Circuits and Systems, pp. 2553-2556, May 2015 [Paper]

• [ISCAS'15] A. Das, Y. Gao, and T. Kim, "An Output Feedback-based Start-up Technique with Automatic Disabling for Battery-less Energy Harvesters," IEEE International Symposium on Circuits and Systems, pp. 233-236, May 2015 [Paper]

• [ISCAS'15] S. Zeinolabedin, A. Do, K.-S. Yeo, and T. Kim, "Design of a Hybrid Neural Spike Detection Algorithm for Implantable Integrated Brain Circuits," IEEE International Symposium on Circuits and Systems, pp. 794-797, May 2015 [Paper]

Journal

• [TCAS-II'15] X. Liu, J. Zhou, C. Wang, K. Chang, J. Lan, L. Liao, Y. Lam, Y. Yang, B. Wang, X. Zhang, W. Goh, T. Kim, and M. Je, "An Ultra-Low-Voltage Sensor Node Processor with Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing Applications," IEEE Transactions on Circuits and Systems-II , Vol. 62, pp. 1149-1153, Dec. 2015 [Paper]

• [TVLSI'15] S. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "An Area and Energy Efficient FIFO Design using Error-Reduced Data Compression and Near-threshold Operation for Image/Video Applications," IEEE Transactions on VLSI Systems, Vol. 23, pp. 2408-2416, Oct. 2015 [Paper]

• [TVLSI'15] T. Kim, P.-F. Lu, K. Jenkins, and C. Kim, "A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology," IEEE Transactions on VLSI Systems, Vol. 23, pp. 1360-1364, July 2015 [Paper]

• [CSSP'15] S. Zeinolabedin, N. Karimi, S. Samavi, and T. Kim, "Structuring of Contourlet Transform for Pipeline-based Implementation," Circuits, Systems & Signal Processing, June 2015 [Paper]

• [MEJ'15] B. Wang, J. Zhou, and T. Kim, "SRAM Devices and Circuits Optimization Toward Energy Efficiency in Multi-Vth CMOS," Microelectronics Journal, Vol. 46, pp. 265-272, Feb. 2015 [Paper]

• [TCAS-I'15] B. Wang, T. Q. Nguyen, A. Do, J. Zhou, M. Je, and T. Kim, "Design of an Ultra-low Voltage 9T SRAM with Equalized Bitline Leakage and CAM-assisted Energy Efficiency Improvement," IEEE Transactions on Circuits and Systems-I, Vol. 62, pp. 441-448, Feb. 2015 [Paper]

2014

Conference

• [A-SSCC'14] A. Do, Z. Lee, B. Wang, I. Chang, and T. Kim, "0.2V 8T SRAM with Improved Bitline Sensing Using Column-based Data Randomization," IEEE Asian Solid-State Circuits Conference, pp. 141-144, Nov. 2014 [Paper]

• [ISOCC'14] [Invited] T. Kim, N. Ba, A. Do, J. Gopal, G. Chua, and P. Singh, "Low Power Memory Design for High Temperature in Ruggedized Electronics," 11th International SoC Design Conference , pp. 110-111, Nov. 2014

• [ISOCC'14] [IEEE CAS Seoul Chapter Award] J. Zhou, X. Liu, C. Wang, K. Chang, J. Luo, J. Lan, L. Liao, Y. Lam, Y. Yang, B. Wang, X. Zhang, W. Goh, T. Kim, and M. Je, "A 0.5V 29pJ/Cycle Sensor Node Processor for Intelligent Sensing Applications," 11th International SoC Design Conference, pp. 70-71, Nov. 2014 [Paper]

• [ISOCC'14] B. Wang and T. Kim, "Ultra-low Power 12T Dual Port SRAM for Hardware Accelerators," 11th International SoC Design Conference, pp. 274-275, Nov. 2014

• [ISCAS'14] S. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "An Area- and Power-Efficient FIFO with Error-Reduced Data Compression for Image/Viedo Processing," IEEE International Symposium on Circuits and Systems, pp. 2277-2280, June 2014 [Paper]

• [ISCAS'14] A. Garg, and T. Kim, "Design of SRAM PUF with Improved Uniformity and Reliability Utilizing Device Aging Effect," IEEE International Symposium on Circuits and Systems, pp. 1941-1944, June 2014 [Paper]

Journal

• [MICRO'14] X. Wang, J. Keane, T. Kim, P. Jain, Q. Tang, and C. Kim, "Silicon Odometers: Compact In-situ Aging Sensors for Robust System Design," IEEE Micro, Vol. 34, No. 6, pp. 74-85, Dec. 2014 [Paper]

• [JSSC'14] [Invited] T. Kim, and N. L. Ba, "Design of a Temperature-Aware Low Voltage SRAM with Self-Adjustable Sensing Margin Enhancement for High Temperature Applications up to 300°C," IEEE Journal of Solid-State Circuits, Vol. 49, pp. 2534-2546, Nov. 2014 [Paper]

• [JSSC'14] [Invited] X. Liu, J. Zhou, Y. Yang, B. Wang, J. Lan, C. Wang, J. Luo, W. L. Goh, T. Kim, and M. Je, "A 457-nW Near-Threshold Cognitive Multi-Functional ECG Processor CMOS for Long-Term Cardiac Monitoring," IEEE Journal of Solid-State Circuits, Vol. 49, pp. 2422-2434, Nov. 2014 [Paper]

• [JMM'14] P. Singh, G. Chua, Y. Liang, J. Gopal, A. Do, and T. Kim, "Anchor-free NEMS Non-volatile Memory Cell for Harsh Environment Data Storage," Journal of Micromechanics and Microengineering, Vol. 24, 115007 (doi:10.1088/0960-1317/24/11/115007), Nov. 2014 [Paper]

• [TCAS-II'14] M. Aung, E. Lim, T. Yoshikawa, and T. Kim, "A 3Gbps/ch Simultaneous Bi-Directional Capacitive Coupling Transceiver for 3DICs," IEEE Transactions on Circuits and Systems-II, Vol. 61, pp. 706-710, Sept. 2014 [Paper]

• [APL'14] G. Chua, P. Singh, B. W.Soon, Y. S. Liang, K. Gopal, T. Kim, and N. Singh, "Molecular Adhesion-Controlled MEMS Memory Device for Harsh Environment Data Storage," Applied Physics Letters, Vol. 105, 113503 (doi: 10.1063/1.4895578), Sept. 2014 [Paper]

• [JSSC'14] [Invited] A. T. Do, C. Yin, K. Velayudhan, Z. C. Lee, K. S. Yeo, and T. Kim, "0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance," IEEE Journal of Solid-State Circuits, Vol. 49, pp. 1487-1498, July 2014 [Paper]

• [TED'14] J. Gopal, A. Do, P. Singh, G. Chua, and T. Kim, "A Cantilever-based NEM Non-volatile Memory Utilizing Electrostatic Actuation and Vibrational Deactuation for High Temperature Operation," IEEE Transactions on Electron Devices, Vol. 61, pp. 2177-2185, June 2014 [Paper]

 2013

Conference

• [A-SSCC'13] [Invited to JSSC] T. Kim and N. L. Ba, "A Low Voltage 8-T SRAM with PVT-Tracking Bitline Sensing Margin Enhancement for High Operating Temperature (up to 300°C)," IEEE Asian Solid-State Circuits Conference, pp. 233-236, Nov. 2013 [Paper]

• [A-SSCC'13] [Invited to JSSC] X. Liu, J. Zhou, Y. Yang, B. Wang, L. Jingjing, C. Wang, J. Luo, W. L. Goh, T. Kim, and M. Je, "A 457-nW Cognitive Multi-Functional ECG Processor," IEEE Asian Solid-State Circuits Conference, pp. 141-144, Nov. 2013 [Paper]

• [A-SSCC'13] B. Wang, J Zhou, K. H. Chang, M. Je,  and T. Kim, "A 0.18V Charge-Pumped DFF with 50.8% Energy-Delay Reduction for Near-/Sub-threshold Circuits," IEEE Asian Solid-State Circuits Conference, pp. 121-124, Nov. 2013 [Paper]

• [ISOCC'13] [Invited] T. Kim, "Overview of Design Techniques for Energy Efficiency Improvement in Advanced CMOS Technology," International SoC Design Conference, pp. 259-262, Nov. 2013

• [ISOCC'13] [Invited] N. Narasimman and T. Kim, "Design Challenges for VCO based ADCs for Ultra-Low Power Operation," International SoC Design Conference, pp. 249-252, Nov. 2013

• [ESSCIRC'13] [Invited to JSSC] A. T. Do, C. Yin, K. S. Yeo, and T. Kim, "Design of a Power-Efficient CAM Using Automated Background Checking Scheme for Small Match Line Swing," IEEE European Solid-State Circuits Conference, pp. 209-212, Sept. 2013 [Paper]

• [ESSDERC'13] A. T. Do, J. K. Gopal, P. Singh, G. L. Chua, and T. Kim, "Design and Array Implementation a Cantilever-based Non-volatile Memory Utilizing Vibrational Reset," IEEE European Solid-State Device Research Conference, pp. 244-287, Sept. 2013 [Paper]

• [ICMAT'13] G. L. Chua, P. Singh, B. W. Soon, T. Kim, J. M. L. Tsai, and N. Singh, "Stiction Controlled MEMS Cantilever for Non-volatile Memory Applications," International Conference on Materials for Advanced Technologies, July 2013

• [ISCAS'13] M. Aung, E. Lim, T. Yoshikawa, and T. Kim, "Design of Self-Biased Fully Differential Receiver and Crosstalk Cancellation for Capacitive Coupled Vertical Interconnects in 3DICs," IEEE International Symposium on Circuits and Systems, pp. 966-969, May 2013 [Paper]

• [ISCAS'13] A. Do, J. Gopal, V. Pott, G. Chua, P. Singh, and T. Kim, "An Improved Read/Write Scheme for Anchorless NEMS-CMOS Non-volatile Memory," IEEE International Symposium on Circuits and Systems, pp.1456-1459, May 2013 [Paper]

• [ISCAS'13] Y. Yeoh, B. Wang, X Yu, and T. Kim, "A 0.4V 7T SRAM with Write Through Virtual Ground and Ultra-fine Grain Power Gating Switches," IEEE International Symposium on Circuits and Systems, pp. 3030-3033, May 2013 [Paper]

Journal

• [TCAS-II'13] Z. C. Lee, K. C. Leong, Z. H. Kong, and T. Kim, "NBTI/PBTI-Aware WWL Voltage Control for Half-Selected Cell Stability Improvement," IEEE Transactions on Circuits and Systems-II, Vol. 60, pp. 602-606, Sept. 2013 [Paper]

• [TCAS-II'13] A. Garg and T. Kim, "SRAM Array Structures for Energy Efficiency Enhancement," IEEE Transactions on Circuits and Systems-II, Vol. 60, pp. 351-355, June 2013 [Paper]

• [JSTS'13] [Invited] T. Kim and Z. Kong, "Impact Analysis of NBTI/PBTI on SRAM VMIN and Design Techniques for Improved SRAM VMIN," Journal of Semiconductor Technology and Science, pp. 87-97, Apr. 2013 [Paper]

• [JSSC'13] K. Chun, H. Zhao, J. D. Harms, T. Kim, J. P. Wang, and C. H. Kim, "A Scaling Roadmap and Performance Evaluation of In-plane and Perpendicular MTJ Based STT-MRAMs for High-density Cache Memory," IEEE Journal of Solid-State Circuits, Vol. 48, pp. 598-610, Feb. 2013 [Paper]

       2012

Conference

• [A-SSCC'12] B. Wang, T. Nguyen, A. Do, J. Zhou, M. Je, and T. Kim, "A 0.2V 16Kb 9T SRAM with Bitline Leakage Equalization and CAM-assisted Write Performance Boosting for Improving Energy Efficiency," IEEE Asian Solid-State Circuits Conference, pp. 73-76, Nov. 2012 [Paper]

• [ISOCC'12] [Invited] T. Kim, B. Wang, and A. Do, "High Energy Efficient Ultra-low Voltage SRAM Design: Device, Circuit, and Architecture," International SoC Design Conference (ISOCC), pp. 367-370, Nov. 2012 [Paper]

• [ISOCC'12] Z. Lee, K. Ho, Z. Kong, and T. Kim, "NBTI/PBTI-Aware Wordline Voltage Control with No Boosted Supply for Stability Improvement of Half-Selected SRAM Cells," International SoC Design Conference, pp. 200-203, Nov. 2012 [Paper]

• [ESSDERC'12] Q. Li, B. Wang, and T. Kim, "A 5.61 pJ, 16 kb 9T SRAM with Single-ended Equalized Bitlines and Fast Local Write-back for Cell Stability Improvement," IEEE European Solid-State Device Research Conference, pp. 201-204, Sept. 2012 [Paper]

• [ASQED'12] A. Do, H. Yi, K. Yeo, and T. Kim, "Retention Time Characterization and Optimization of Logic-compatible Embedded DRAM Cells," Asia Symposium on Quality Electronic Design, pp. 29-34, July 2012 [Paper]

• [ASQED'12] B. Wang, J. Zhou, and T. Kim, "Maximization of SRAM Energy Efficiency Utilizing MTCMOS Technology," Asia Symposium on Quality Electronic Design, pp. 35-40, July 2012 [Paper]

• [ISCAS'12] T. Kim, P. Lu, and C. Kim, "Design of Ring Oscillator Structures for Measuring Isolated NBTI and PBTI," IEEE International Symposium on Circuits and Systems, pp. 1580-1583, May 2012 [Paper]

• [IRPS'12] R. Vaddi, V. Pott, J. Lin, and T. Kim, "Design and Analysis of Anchorless Shuttle Nano-electro-mechanical Non-volatile Memory for High Temperature Applications," IEEE International Reliability Physics Symposium, pp. ME.3.1-ME.3.6, Apr. 2012 [Paper]

• [ICSIC'12] R. Vaddi, V. Pott, J. Lin, and T. Kim, "Design, Modeling and Simulation of an Anchorless Nano-Electro-Mechanical Nonvolatile Memory for High Temperature Applications," International Conference on Solid-State and Integrated Circuit, pp. 12-17, Mar. 2012

• [3DIC'12] M. Aung, E. Lim, T. Yoshikawa, and T. Kim, "Design of Capacitive-Coupling-Based Simultaneously Bi-directional Transceivers for 3DIC," IEEE International 3D System Integration Conference, pp. 1-4, Feb. 2012 [Paper]

Journal

• [TCAS-II'12] [Special Issue] A. Do, Q. Truc, K. Yeo, and T. Kim, "Sensing Margin Enhancement Techniques for Ultra-low Voltage SRAMs Utilizing Bitline Boosting Current and Equalized Bitline Leakage," IEEE Transactions on Circuits and Systems-II, Vol. 59, pp. 868-872, Dec. 2012 [Paper]

• [EDL'12] R. Vaddi, V. Pott, G. Chua, J. Lin, and T. Kim, "Design and Scalability of a Memory Array Utilizing Anchor-free Nano-electro-mechanical Non-volatile Memory Device," IEEE Electron Device Letters, Vol. 33, pp. 1315-1317, Sept. 2012 [Paper]

• [EDL'12] V. Pott, R. Vaddi, G. Chua, J. Lin, and T. Kim, "Design optimization of a pulsed-mode electromechanical non-volatile memory," IEEE Electron Device Letters, Vol. 33, pp. 1207-1209, Aug. 2012 [Paper]

• [JETCAS'12] M. Aung, E. Lim, T. Yoshikawa, and T. Kim, "Design of Simultaneous Bi-directional Transceivers Utilizing Capacitive Coupling for 3DICs," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, pp. 257-265, June 2012 [Paper]

• [TED'12] V. Pott, G. Chua, R. Vaddi, J. Lin, and T. Kim, "The shuttle nano-electro-mechanical non-volatile memory," IEEE Transactions on Electron Devices (TED), Vol. 59, pp. 1137-1143, Apr. 2012 [Paper]

• [TCAS-I'12] T. Kim, W. Zhang,  and C. Kim, "An SRAM Reliability Test Macro for Fully-Automated Statistical Measurement of VMIN Degradation," IEEE Transactions on Circuits and Systems-I, Vol. 59, pp. 584-593, Mar. 2012 [Paper]

       2011

Conference

• [C22] R. Vaddi and T. Kim, "Ultra-low Power High Efficient Rectifiers with 3T/4T Double-gate MOSFETs for RFID Applications," International Symposium on Integrated Circuits, pp. 611-614, Dec. 2011

• [ISOCC'11] [IEEE SSCS Seoul Chapter Award][Invited to JSTS] T. Kim and Z. Kong, "Impacts of NBTI/PBTI on SRAM VMIN and Design Techniques for SRAM VMIN Improvement," International SoC Design Conference, pp. 163-166, Nov. 2011 [Paper]

• [ISOCC'11] Q. Li and T. Kim, "Analysis of SRAM Hierarchical Bitlines for Optimal Performance and Variation Tolerance," International SoC Design Conference, pp. 412-415, Nov. 2011

• [IRPS'11] J. Kim, B. Linder, R. Rao, T. Kim, P. Lu, K. Jenkins, C. Kim, A. Bansal, S. Mukhopadhyay, and C. Chuang, “Reliability Monitoring Ring Oscillator Structures for Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies,” IEEE International Reliability Physics Symposium, pp. 47-50, Apr. 2011 [Paper]

Journal

• [JLPEA'11] R. Vaddi, R. P. Agarwal, S. Dasgupta, and T. Kim, "Design and Analysis of Double-gate MOSFETs for Ultra-low Power Radio Frequency Identification (RFID): Device and Circuit Co-design," Journal of Low Power Electronics and Applications, pp. 277-302, July 2011 [Paper]

       2010

Conference

• [APCCAS'10] Q. Li and T. Kim, “A 9T Subthreshold SRAM Bitcell with Data-independent Bitline Leakage for Improved Bitline Swing and Variation Tolerance,” IEEE Asia Pacific Conference on Circuits and Systems, pp. 260-263, Dec. 2010 [Paper]

Journal

• [MRJ'10] [Invited] J. Keane, T. Kim, X. Wang,  and C. Kim, "On-Chip Reliability Monitors for Measuring Circuit Degradation," Microelectronics Reliability Journal, Vol. 50, pp. 1039-1053, Aug. 2010 [Paper]

• [TVLSI'10] J. Keane, T. Kim, and C. Kim, “An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation,” IEEE Trans. on VLSI Systems, Vol. 18, No. 6, pp. 947-956, June 2010 [Paper]

2006 ~ 2009

Conference

• [CICC'09] Tae-Hyoung Kim, Wei Zhang, and Chris Kim, “An SRAM Reliability Test Macro for Fully-Automated Statistical Measurements of Vmin Degradation,” IEEE Custom Integrated Circuits Conference, pp. 231-234, Sep. 2009 [Paper]

• [ICCAD'08] John Keane, Tae-Hyoung Kim, and Chris Kim, ”Silicon Odometers: On-Chip Test Structures for Monitoring Reliability Mechanisms and Sources of Variation,” Workshop on Test Structure Design for Variability Characterization in Conjunction with IEEE International Conference on Computer-Aided Design, Nov. 2008 [Paper]

• [CICC'08] [AMD/CICC Student Scholarship Award] Tae-Hyoung Kim, Jason Liu, and Chris Kim, “A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode,” IEEE Custom Integrated Circuit Conference, pp. 407-410, Sep. 2008 [Paper]

• [ISLPED'08] Pulkit Jain, Tae-Hyoung Kim, John Keane, and Chris Kim, “A Multi-Story Power Delivery Technique for 3D Integrated Circuits,” IEEE International Symposium on Low Power Electronics and Design, pp. 57-62, Aug., 2008 [Paper]

• [ISCAS'08] [Invited] Tae-Hyoung Kim, Jason Liu, John Keane, and Chris Kim, “Circuit Techniques for Ultra-Low Power Sub-threshold SRAMs,” IEEE International Symposium on Circuits and Systems, pp. 2574-2577, May 2008 [Paper]

• [CICC'07] Tae-Hyoung Kim, Jason Liu, and Chris Kim, “An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement,” IEEE Custom Integrated Circuits Conference, pp. 241-244, Sep. 2007 [Paper]

• [ISLPED'07] John Keane, Tae-Hyoung Kim, and Chris Kim, “An On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation,” IEEE International Symposium on Low Power Electronics and Design, pp. 189-194, Aug. 2007 [Paper]

• [SOVC'07] [DAC/ISSCC Design Contest Winner][Invited to JSSC] Tae-Hyoung Kim, Randy Persaud, and Chris Kim, “Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits,” IEEE Symposium on VLSI Circuits, pp. 122-123, June 2007 [Paper]

• [ISSCC'07] Tae-Hyoung Kim, Jason Liu, John Keane, and Chris Kim, “A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual-Ground Replica Scheme,” IEEE International Solid State Circuits Conference, pp. 330-606, Feb. 2007 [Paper]

• [ISLPED'06] Tae-Hyoung Kim, Hanyong Eom, John Keane, and Chris Kim, “Utilizing Reverse Short Channel Effect for Optimal Subthreshold Circuit Design," IEEE International Symposium on Low Power Electronics and Design, pp. 127-130, Oct. 2006 [Paper]

• [DAC'06] John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin Sapatnekar, and Chris Kim, “Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing,” IEEE Design Automation Conference, pp. 425-428, July, 2006 [Paper]

Journal

• [JSSC'09] Tae-Hyoung Kim, Jason Liu, and Chris H. Kim, “A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode,” IEEE Journal of Solid State Circuits, Vol. 44, No. 6, pp. 1785-1795, June 2009 [Paper]

• [TVLSI'08] John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin Sapatnekar, and Chris Kim, “Stack Sizing for Optimal Current Drivability in Subthreshold Circuits,” IEEE Trans. on VLSI Systems, Vol. 16, No. 5, pp. 598-602, May 2008 [Paper]

• [JSSC'08] [Invited] Tae-Hyoung Kim, Randy Persaud, and Chris Kim, “Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits,” IEEE Journal of Solid State Circuits, Vol. 43, No. 4, pp. 874-880, Apr. 2008 [Paper]

• [JSSC'08] Tae-Hyoung Kim, Jason Liu, John Keane, and Chris Kim, “A 0.2V, 480kb Subthreshold SRAM with 1k Cells per Bitline for Ultra-Low Voltage Computing,” IEEE Journal of Solid State Circuits, Vol. 43, No. 2, pp. 518-529, Feb. 2008 [Paper]

• [TVLSI'07] Tae-Hyoung Kim, John Keane, Hanyong Eom, and Chris Kim, “Utilizing Reverse Short Channel Effect for Optimal Subthreshold Circuit Design,” IEEE Trans. on VLSI Systems, Vol. 15, No. 7, pp. 821-829, July, 2007 [Paper]

2000 ~ 2005

Conference

• [ISCAS'05] Tae-Hyoung Kim, Uk-Rae Cho, and Hyun-Geun Byun, “A 1.2V Multi Gb/s/pin Memory Interface Circuits with High Linearity and Low Mismatch,” IEEE International Symposium on Circuit and System, pp.1847-1850, May, 2005

• [AP-ASIC'04] [Invited to IEICE] Tae-Hyoung Kim, Uk-Rae Cho, and Hyun-Geun Byun, “A High Resolution, Wide Range Digital Impedance Controller for High-Speed SRAM Interface,” IEEE Asia-Pacific Conference on Advanced System IC (AP-ASIC), pp. 120-123, Aug., 2004

• [ISSCC'03] [Invited to JSSC] Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, et al., “A 1.2V 1.5Gbps 72M DDR3 SRAM,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 300-494, Feb., 2003

• [KCS'01] Tae-Hyoung Kim, Woong Joo, Jun-Jey Sung, Seung-Bin You, and Suki Kim, “An 8-Bit 40MSamples/s Low Power Folding & Interpolating ADC,” IEEK Korea Conference on Semiconductor (KCS), Feb. 2001

• [AP-ASIC'00] Tae-Hyoung Kim, Jun-Jey Sung, Soo-Hwan Kim, Woong Joo, Seung-Bin You, and Suki Kim, “A 10-bit 40Msamples/s Cascading Folding & Interpolating A/D Converter with Wide Range Error Correction,” IEEE Asia-Pacific Conference on Advanced System IC (AP-ASIC), pp. 57-60, Aug., 2000

• [KCS'00] Tae-Hyoung Kim, Jun-Jey Sung, Soo-Hwan Kim, Shin-Il Lim, and Suki Kim, “A 10-Bit, 40MSamples/s, Fully Nyquist Rate and Folding & Interpolating ADC with a Cascading Architecture,” IEEK Korea Conference on Semiconductor, Jan., 2000

 Journal

• [IEICE'05] [Invited] Tae-Hyoung Kim, Kwang-Jin Lee, Uk-Rae Cho, and Hyun-Geun Byun, “A High Resolution, Wide Range Digital Impedance Controller,” IEICE Trans. on Electronics, Vol. E88-C, pp. 1723-1725, Aug. 2005

• [ETRI'05] [ETRI Journal Paper of the Year] Kwang-Jin Lee, Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun, and Suki Kim, “Voltage-mode 1.5Gbps Interface Circuits for Chip-to-Chip Communication,” ETRI Journal, Vol. 27, Number 1, pp. 81-88, Feb., 2005

• [JSSC'03] [Invited] Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, et al., “A 1.2V 1.5Gbps 72M DDR3 SRAM,” IEEE Journal of Solid State Circuits (JSSC), Vol. 38, pp. 1943-1951, Nov., 2003

• [JKPS'02] Mingi Kim, Tae-Hyoung Kim, Woong Joo, et al., “Low Power, 8-bit 40Msamples/s A/D Converter with a Wide Range Error Correction Scheme,” Journal of Korea Physics Society, Vol. 40, No. 1, pp. 11-16, Jan., 2002

• [ASIC'00] Tae-Hyoung Kim, Jun-Jey Sung, Soo-Hwan Kim, Shin-Il Lim, and Suki Kim, “A 10-bit, 40-MSamples/s, Folding & Interpolating ADC with Wide Range Error Correction,” Journal of the Research Institute of ASIC Design, Aug. 2000