What's happening

August 2023 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 1.5), release of the PC based Inmos Transputer T425 Rev. C VBC emulator (version 0.7) and release of the PC based Inmos Transputer T805 Rev. D VBC emulator (version 0.1). Also releases for macOS (64-bit). The T805 VBC emulator is new. The T800 VBC emulator has had a bug fix in the FPU to resolve a problem seen when running the savage test bench. The T425 VBC emulator and T800 VBC emulator both had bug fixes in the link engine.

February 2021 to July 2023

T800 VBC emulator updates - the latest version 1.4 has had minor changes to the FPU code within the T800 VBC emulator in order to removed all the horrible tricks and correct the FPU constants. As a result the FPU timings are much closer the real T800 transputer hardware, and now is aligned with the ucode definitions defined within T800 ucode proof document on David May’s website. A version is available for the PC and macOS (64-bit).

T425 VBC emulator updates - the latest version 0.6 has had major rework comprising of a new ALU design, based on analysis of the ucode column drivers. The new ALU no longer has an adder/subtractor but simply uses logic functions (which can be formed into xor paths) as was done in the real transputer hardware. Secondly, the hardware interrupt mechanism has had a complete rework based on further analysis and understanding of the ucode. A further understanding of the ucode has allowed a number of earlier horrible tricks to be removed from the VBC emulator code, including a rework of the byte move logic. The latter came about by chance after I spotted a previously unidentified function associated with the DataReg and the previous read register (PrevReadReg), when analysing the gcall and ret instructions. Lastly a number of bug have been fixes which were in the previous version. A version is available for the PC and macOS (64-bit).

What’s happening next:

As for the T414 VBC emulator and T800 VBC emulator, I do not intend to support or maintain these any further. As such they will not receive any further updates. Technically these two emulators will be retired. They will follow the same lifecycle as the jserver, which is also now retired.

As for future plans and activities, I am intending to start the design of a T805 VBC emulator. This will require some pre work but it should be helped by my knowledge of the T425 VBC emulator and the T800 FPU.

I hope to have a working version of the T805 VBC emulator within the next 1-2 months. I will continue to support the T425 VBC emulator and fix any bugs reported by users.

December 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 1.3).  Fixed many subtle bugs in an effort to get the emulator to pass the FPU Validation Suite, written by Mike Brustle. The latest release now passes all the fpu validation tests. Fixed bug in the unpacketizer logic (data into FPU from IU) which was causing problems when switching tasks of different priorities. As a result the high priority intruppting mechanism now fully works on the FPU. The T800 VBC emulator is now complete. Merry Christmas. 

November 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 1.2).  Fixed bugs in support logic for FPUDIV and FPUMUL instructions, which was causing some 64-bit double precision calculations to be out by a single lsb. As a result the savage test bench now generates the same results as the REAL T800. All FPU instructions are now fully implemented.

November 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 1.1).  Fixed the bug causing some 64-bit double precision calculations to be out by a single lsb. 

October 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 1.0). Debugged and integrated the FPUSQRT instruction consisting of three ucodes: FPUSQRTFIRST, FPUSQRTSTEP and FPUSQRTLAST.  Debugged and integrated the FPUREM instruction consisting of two ucodes: FPUREMFIRST and FPUREMSTEP. These instructions is now fully working and calculating the same results as the REAL transputer, for both 32-bit single precision data format and 64-bit double precision data formats. It should be noted that there is a rounding constant or other logic bug causing an extra lsb in some of the 64-bit double precision calculation results, which I intend to fix in the next release.

September 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 0.9). Debugged and integrated the fpudiv instruction. The fpudiv instruction is now fully working and calculating the same results as the REAL transputer, for both 32-bit single and 64-bit double precision data formats.

September 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 0.8). Debugged and integrated the fpumul instruction. The fpumul instruction is now fully working and calculating the same results as the REAL transputer, for both 32-bit single and 64-bit double precision data formats.

August 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 0.7). Debugged and integrated the fpi32tor64 instruction. Started adding some of the missing vbc column driver logic for supporting the FPUMUL instruction. Spent some time investigating the mulstep function to understand effects on the FPU registers. Note the FPUMUL instruction does not work yet.

August 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 0.6). The fpur64tor32 instruction now successfully works.

August 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 0.4). Added missing constants to allow fpi32tor32 and fpur32tor64 instructions to successfully work. Note the fpur64tor32 instruction may not work yet. Debugged and integrated the remaining FPU test support instructions: fputestldr, fputestldt, fputestlds, fputeststr, fputeststt and fputeststs.

July 2020 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 0.3).

The T800 VBC emulator is now successfully running code on the FPU co-processor, using the FPU uCode extracted from the REAL T800 Rev. D device (see tab Inmos T414B uCode ROM). The T800 FPU emulator has limited operation, but the FPUADD and FPUSUB instructions are now fully working and calculating the same results as the REAL transputer, for both 32-bit single and 64-bit double precision data formats. Over the last couple of months I have finished adding the missing FPU exponent data-path and fractional data-path. This has comprised of the combined normaliser and shifter, the rounding logic, the exponent constants and the 13-bit and 59-bit ALUs. The FPU processor emulation is done in circa. 2000 lines of C code. In addition to the fpuadd and fpusub instructions, the fpgt instruction and the fpu loading and saving instructions are working. The next integration phase will be adding the fpumul and fpudiv instruction support.

April 2020 - A few months ago I started porting the T414 VBC emulator to run the T800 Integer Unit (IU) uCode which I had extracted from a REAL T800 Rev. D device (see tab Inmos T414B uCode ROM). The porting and testing went well and I soon had the T800 VBC emulator running all my Occam test code. After that I made a start by adding the memory transfers to the FPU datain and dataout registers. Well even more good news. The T800 VBC emulator is now running code on the FPU processor, using the real FPU uCode extracted from real T800 device.

Over the last month I’ve managed to get the FPU micro-controller integrated and working (including STEP operation), basis FPU stack handling added, instruction passing from the IU to the FPU, adding of the FPU logic to control the IU aborting, un-packetization and packetization of data between Data I/O registers and the FPU registers (and visa versa). The long and short now means some basic FPU instructions are now working. The fpsttest and fpldtest instructions have successfully been run and generated the correct results as the REAL T800.

February 2020 – I have spent the last few months analysing and decoding both the Inmos T800 Integer Unit (IU) and the Inmos T800 Floating Point Unit (FPU) ucode columns. The task has gone better than I ever expected. Right now, all the T800 IU ucode columns are fully known and defined. For the T800 FPU column ucode most are now known with only a few bits of logic still to be determined.

To help my investigations, I manually decoded (a very painful task!) all 68 ucode entries of the FPUADD instruction. The task of decoding the FPU ucode has been much harder than the IU. Firstly, the FPU ucode was generated by a different team of Inmos engineers (lead by Fred Homewood), whereas the IU microcode was led by Guy Harriman, secondly there is little in common between the operation of the IU and the FPU, and thirdly there is very little if any documentation defining the FPU internals.

To help me understand the FPU ucode, I have used the extract FPU microcode from the T800 FPU Rev. D (see my website for further details) and the T800 FPU proof document (containing parts of the Rev. B FPU ucode) available on Dave Mays website.

In parallel, I have been documenting the FPU hardware and data-path logic based on my findings. I am nearly at a point where I could write the C code for the full T800 VBC emulator (combining both IU and FPU processors).

November 2019 - Release of the PC based Inmos Transputer T425 Rev. C VBC emulator (version 0.5) and release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.9). 

The main focus of the recent updates has been to get the VBC emulator to match the results of the Whetstone benchmark test. This has been a very time consuming task. Whilst the latest emulator results are not the same as the REAL Transputer, the results are close enough to now calling it a day. There are many factors which contribute to the timing and it could take years to find the answer for very little gain (it’s like looking for a needle in the hay stack)!

Hence, I’m happy to say that the two VBC emulators are now working well enough to call it a day. There will be no further planned updates to the T414 and T425 VBC emulators.

The following are a list of T414emu changes made between version 2.7 and 2.9:

Bug fix in Error flag detection logic . Added statistics support (/su) in pro build. Added IregSlave changes to correct loading of pre-fetch buffer. Added IB and IB pre-fetch optimisations. Added memory speed-up to allow CPU to continue executing instructions after write actioned to memory interface, until at least next memory access. Added bug fix in the /SJ display caused by invalid IB after J,CJ instructions. Added CPU and memory bus trace analysis dump (/u /su) in pro build. Added /sn and /n to disable the IB and IB pre-fetch optimisations. Added emulation of refresh external cycle. Many changes to get Whetstone benchmark timing closer to the REAL transputer. Bug fix in abort logic by adding missing STEPinstruction term. Bug fix in vbc dump in pro build.

The following are a list of T425emu changes made between versions 0.3 and 0.5:

Bug fix in Error flag detection logic. Added fix to change write masking of Status Register to access all debugging/break-point bits. Added statistics support (/su) in pro build. Added IregSlave changes to correct loading of pre-fetch buffer. Added missing timeslice logic, which had been incorporated in T414 but not T425. Added IB and IB pre-fetch optimisations in pro build. Added memory speed-up to allow CPU to continue executing instructions after write actioned to memory interface, until at least next memory access. Added bug fix in the /SJ display caused by invalid IB after J,CJ instructions. Added CPU and memory bus trace analysis dump (/u /su) in pro build. Added /sn and /n to disable the IB and IB pre-fetch optimisations. Added emulation of refresh external cycle. Many changes to get Whetstone benchmark timing closer to the REAL transputer. Bug fix in abort logic by adding missing STEP instruction. Bug fix in vbc dump in pro build.

August 2019 - Release of the PC based Inmos Transputer T425 Rev. C VBC emulator (version 0.3) and release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.7). The updates fixed bugs identified during the running of FTEST (part of old Occam check program later used in ispy) on the T414 VBC emulator, in order to get it to fully pass the test.

August 2019 - Release of the PC based Inmos Transputer T425 Rev. C VBC emulator (version 0.2). The update fixes bugs to get the instructions crcword, crcbyte and bitrevnbits to pass the TVS test.

August 2019 - Public release of the PC based Inmos Transputer T425 Rev. C VBC emulator (version 0.1). 

June 2019 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.6). The following are a list of T414emu changes made between v2.5 and v2.6 over the period of March 2019 to June 2019:

In pro build, added /sm and /sd options to select external memory size (1-4MBytes) and disable internal SRAM. Add additional ctrl-c options, namely toggling of v and r for sending test byte into linkIn1 of t414. Bug fixes when high priority timer or channel interrupting low priority task. The ByteWriteStrobeEnable Latch was being wrongly cleared before any BYTE writes had finished when handling a switch to high priority task in the ucode.

In pro and std builds, improvement to /sj option for CJ, J and CALL. Added ability to send test byte into link 1 input in order to support testing. Bug fix to processorcyclescount updates. Minix v1.5 works again with /sx 6 option. Bug fix to ensure s_TwoReadsLatch is computed done every cycle. Bug fix for when high priority H/W request (i.e. from channel or timer) interrupts low priority move instruction. In particular the fix affected the two reads case. Change to timeslice logic to work by means of two negative edges on CLOCKslave[9], as per details in test414a.occ.

In pro and std builds, added displaying of processor cycle count in /sj option. In pro and std builds changed switch from /si to /sk for display host communications, in order to free up /si for iserver verbose mode. Minor change to DataMemAddrfromZ logic and display of VBC output listing, based on REAL T414B test results (Thanks Mike! for remote access to T414B device). Updated the /sz output format to align with ISERVER output style. Added /si switch support (partial) and the famous "Booting root transputer..." message.

Now I'm happy to call it a day with the T414 VBC emulator. Next up the T425 VBC emulator which is currently in beta testing phase.

March 2019 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.5). I was going to call it a day but I just had to fix the last few things. These as it happened were a real headache to fix.

The changes included a few bug fixes. A major rework of the memory access controller to operate a delayed pipeline method so that the ldl and stl instructions execution matched the correct number of instruction cycles (i.e. as per Transputer Databook). An updated of the bus arbiter to include the missing link interface requests so the arbiter now fully and correctly handles all memory requests. And lastly, a rework of the instruction streamer to improve request access timing.

July 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.4). Various tidy-ups including removal of some code left over from early debugging. Now I'm happy to call it a day with the VBC emulator.

July 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.3). Added missing AregReadPartWrite logic in the byte move logic as a results of exhaustive byte move Occam test bench testing on REAL T414B Transputer. Thanks to Mike Brustle for access to remote T414B device for testing.

July 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.2). Fixed a bug in the byte move logic as a results of writing an exhaustive byte move Occam test bench. It was a tricky one to locate and fix.

June 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.1).

The month was busy spent updating the memory interface timing and bus arbitration logic.

Changes (major) were made to the memory interface and bus arbiter, in order to update the memory interface timings to correctly handle instruction pre-buffer register loading in the background (when ucode instructions were not requesting memory accesses) and also to update correct emulation cycles for internal and external accesses. Extra switch options added to support this feature in the Pro build. Quite a lot of effort!

Changes (major) were made to correctly implement the mechanism for handling of a high priority timer alarm request or channel run or ready request interrupting a running low priority. The previous scheme worked but timing details in the Inmos Transputer data book indicated that there was a faster (i.e. lower interrupt latency route) method for high priority requests to be serviced.

Other minor changes were to the link engine (non-functional) in order to update the naming convention of the priority latches used in the Input and Output channels.

As a result of these changes the Minix OS now runs on the VBC emulator!

June 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 2.0). Fixed a bug in configuring DataMemAddress register, as a result of incorrect ucode decoding. The major change was adding the /SQ option support in the Lite build to allow faster emulation. Minor banner changes to include SQ and SZ options.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.9). Fixed a bug to correctly the setting of the previous read address register, which was previously being corrupted due to incorrect ucode implementation.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.8). Fixed a tricky bug in the byte move logic which meant that a few move instruction source/destination combinations failed. The good news is this fix now means that the C code .btl files (compiled using Inmos C toolset d7214c) now run successfully (for Mike!). Secondly, the Inmos Occam toolset tools also display their banner screens.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.7). Fixed a bug with the timer alarm comparator logic.

Over the last month I have been testing various Occam test cases (compiled using Occam toolset d7205a) to check operation of the VBC emulator. The test cases have got more and more complex. The most recent Occam test case consisted of a number of processes running timers at both high and low priority, whilst a continuous low priority data move transfer was happening in the background and checking its its destination data after completion for any corruption. Each of the timer processes was used to communicate with a "alt" driven handler and display various status outputs throughout the test. This complex test has helped to identify various bugs.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.6). More bug fixes to sort a register corruption problem caused by back to back read cycles during the return from high priority interrupt.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.5). Fixed a bug in the high priority interrupt mechanism during a low priority move instruction execution.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.4). Fixed a bug in the conditional "ready not run" logic in order to correct a loss of link input data bytes. This fixed problems with running both prime and square root code examples.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.3). Added missing /SZ option in the Lite build. Fixed a bug in the subsystem control logic to correctly clear run request latches.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.2). Fixed a bug in the memory dump feature.

May 2018 - Release of the PC based Inmos Transputer T414 Rev. B VBC emulator (version 1.1).

May 2017 - Release of the PC based T414 Transputer emulator (jserver version 5.8). Updated gajw instruction (note: no functional change from version 5.7 except the adding of missing warning message). Added correct solutions for cword and xword instructions based on T414 ucode analysis.   

December 2016 - Spent time decoding the ucode ROM bits in the Inmos T414B device (see Inmos T414B uCode ROM tab).

November 2016 - Extracting more ucode data from the ROM in the Inmos T414B device (see Inmos T414B uCode ROM tab).

October 2016 - After 1 year and 5 months of head scratching, dead ends and lots of effort I have finally successfully extracted all the ROM contents from the Inmos T414B device (see Inmos T414B uCode ROM tab).

September 2016 - Latest update and some finding of my investigation to extract the ucode from the ROM in the Inmos T414B device (see Inmos T414B uCode ROM tab).

August 2016 - Whilst I have not updated my website recently, I have made some more progress with my project to read the ucode out of the Inmos T414B device.

The updated FPGA design version 60 (or Mk 60) and fuse files are ready and I've got the test vector files all prepared to fire at the target to try and extract ucode. I'm just waiting for the hardware platform to be modified to bring it in-line with the schematic on the website (see Inmos T414B uCode ROM tab).

The board should be ready in the next week or so and I'll be able to try out my latest ideas based on the discussions with Jon Beecroft. Any news and I’ll update this website.

Whilst I've been twiddling my thumbs I've done a port of jserver, s42ma and s42emu to the Mac OSX. I've successfully compiled, linked Occam code using the Inmos Occam toolset and run .btl code on the Mac OSX. It should be noted that the jserver build is fully functional except for the multiprocessor support (/sn) which is not included at present. If anyone is interested in running the Inmos Occam toolset on a Mac, then please let me know and I’ll make the build public.

Since May 2015, I've started an on-going project to access the uCode stored in the internal ROM inside the Inmos T414B Transputer device. Refer to Inmos T414B uCode ROM tab for more details.

March 2015 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator for the Mac OS X. (version 0.8 beta).

January 2015 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator, initially for the PC. (version 0.8 beta). Added emulation of Interface Control logic and memory interface. VBC cycles are now aborted if a memory access is required. Fixed incrementor to MADDR path in the emulator. Added correct handling of ForceFetch signal.

December 2014 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator, initially for the PC. (version 0.7 beta). Added memory dump option /m to support instruction verification testing.

November 2014 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator, initially for the PC. (version 0.6 beta). Correction to decoder function to ensure DA, FN and EntryAddress computed in source phase. Reposition register debug statements to end of source phase (was wrongly positioned at start). Correction to /d switch register and internal signal debug statements to ensure MAddrReg correctly updated if altered in destination phase. Display the MIR status on every cycle (was viewed via /d switch). Fix to read and write byte functions to include the lsb in the upperlower latch. Added missing right shift of lsb of Aregslave into upperlower latch (found during lb instruction testing).

November 2014 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator, initially for the PC. (version 0.5 beta). Improvements in diagnostics output for register contents during source and destination phases of instruction cycle.

November 2014 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator, initially for the PC. (version 0.4 beta). Fixed VBC for LDTI, WAIT, PSE, RET, DIV and MOVE instructions.

November 2014 - Made corrections to LDTI, WAIT, PSE, RET, DIV and MOVE instructions in order to fix same cut and paste error I had wrongly done in MUL and TLNG during the initial pdf to text / compile of the VBC. I’ve updated the zip file at the bottom of the Inmos S42 webpage.

November 2014 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator, initially for the PC. (version 0.3 beta). Fixed TLNG instruction and the TLNG copy used in the MUL instruction.

November 2014 - Whilst performing instruction verification testing on the Inmos Simple 42 emulator, I found in the microcode (or VBC) for the TLNG instruction a cut and paste I had wrongly done during the initial pdf to text / compile of the VBC. Also corrected the same mistake in the TLNG copy in the MUL instruction. I’ve updated the zip file at the bottom of the Inmos S42 webpage.

October 2014 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator, initially for the PC. (version 0.2 beta). Fixed MUL instruction.

October 2014 - Release of the Inmos Simple 42 (or S42 for short) prototype Transputer emulator, initially for the PC. (version 0.1 beta)

October 2014 - Whilst performing instruction verification testing on the Inmos Simple 42 emulator, I found a mistake in the microcode (or VBC) for the SL instruction. The VBC was missing CfromZ, in order to update the shifted C register. I’ve updated the zip file at the bottom of the Inmos S42 webpage.

October 2014 - Whilst performing instruction verification testing on the Inmos Simple 42 emulator, I found a mistake in the microcode (or VBC) for the TLNG instruction. The VBC wrongly stated NoCarry but it should have been CarryfromAslave15. I’ve updated the zip file at the bottom of the Inmos S42 webpage.

October 2014 - Whilst performing instruction verification testing on the Inmos Simple 42 emulator, I found a mistake in the microcode (or VBC) for the CLC instruction. The VBC wrongly had the A register being cleared instead of the C register. I’ve updated the zip file at the bottom of the Inmos S42 webpage.

October 2014 - The first bit of good news is all the C code is written for the Inmos Simple 42 emulator. Secondly, I have spent the last month verifying the instructions within the Simple 42 emulator. I’ve completed about 39% of the task so far. I ran into problems with the udiv instruction. I finally got it working after help from Roger Shepherd who remembered that the original signed divide instruction (div) was intended to use a signed non-restoring divider algorithm. However, there were problems during the design and the final div solution in the Simple 42 used the udiv code and a wrapper to handle the register sign bits. The S42 Divide Step Control Logic in the S42ENGDOC (on David May’s website) is still showing the logic for the signed non-restoring divider algorithm. I’ve updated the block diagrams to correct the oversight on my S42 webpage. Once I made the necessary correction in the Simple 42 emulator the udiv instruction executed correctly.

The following is a list of the instructions verified so far:

J, LDL, PFIX, NFIX, REV, GT, AND, OR, XOR, CLC, STAC, ADD, ADDC, SUB, SUBC, UMUL, DIV and UDIV.

The MUL instruction requires a fix to CShiftin15fromArithLogic in the C code determineShiftRightC function. This equation is not defined anywhere and will require some test cases to determine prior to instruction verification testing.

I am planning to release the Simple 42 emulator for public use on my website with executable binaries for both PC Win32 console and Mac OSx platforms, when I have completed around 50%-60% of the instruction verification testing. This should be before the end of the year. If anyone wants a beta release then please contact me (email address on my home transputer emulator webpage).

September 2014 - I've started writing an Inmos Simple 42 emulator. The S42 (for short) emulator will execute the output microcode from my Inmos Simple 42 microcode assembler. I've written all the code to emulate the data paths, the registers, alu, conditional logic, the micro controller and the memory access controller.

Using a very simple program to load to constants into the Areg and Breg, add them, add another constant and then reverse the Areg and Breg, the S42 emulator loaded the binary file and ran it correctly. Whilst I was debugging the code, I found an error in the S42 microcode assembler output (which is available on my website) as the add instruction was only appearing to add the lower 12-bits and not all 16-bits. I eventually traced the bug to an incorrectly entered microcode line, which I had done when converting the PDF to text. The offending vbc signals were on the same line as the instruction label and we're being ignored. Once I moved them onto the correct next line and reran the S42 microcode assembler and used the new output file in the S42 emulator build then all was ok and the add instruction correctly worked. I also found the same bug in the XOR instruction and one other which I can't recall now. I've uploaded the new files to my S42 webpage.

So I've still a lot to do - add shift logic, destination disable logic, finish the conditional logic (bits 0 & 1) for the next microcode in a conditional jump, add the c register logic. Hopefully I'll be able to do a little more over the next month.

March 2014 - Updated (version 0.3 beta now on my website) the simple 42 microcode assembler (aka VBC reader) to include banner changes, displays conditional and non-conditional jump address allocation in diagnostics (/d) output and added fully functional automated feedback address table generator (opposed to the pre-computed table in version 0.1). Click on the Inmos S42 tab for more details.

March 2014 - I've written a simple 42 microcode assembler (otherwise known as 'vbc reader' to ex-Inmos employees) to allow the simple 42 microcode vbc available on Dave May's website to create a S42 microcode ROM output (in a c header style format). Click on the Inmos S42 tab for more details.

November 2013 - Release of a combined 3L afserver / transputer emulator, called jafserver (version 0.5 beta) and also updated the supporting driver exe tools for use with 3L C.

November 2013 - Release of a combined 3L afserver / transputer emulator, called jafserver (version 0.4 beta). Corrected program exit codes.

November 2013 - Release of a combined 3L afserver / transputer emulator, called jafserver (version 0.3 beta). Minor bug fix.

November 2013 - Release of a combined 3L afserver / transputer emulator, called jafserver (version 0.2 beta). It will allow the 3L C, pascal and fortan compilers to run. Click on the 3L afserver tab for more details.

October 2013 - I was asked to see if I could get the 3L C compiler, linker and afserver tools to run with the transputer emulator. The original method I decided to use was a quick fix to allow the tools to be integrated without too much effort or prior afserver protocol knowledge, by using the multiprocessor support capability of jserver. A transputer emulator was run in one Win32 console (using the /SN 1 option) whist a modified 3L afserver (incorporating the necessary LCM interface) was run in second Win32 console. A fully working 3L afserver / transputer emulator was achieved, but unless you were using a fast PC (i.e.  Intel i7) the emulation was far too slow. I later dropped this approach and set about creating a combined 3L afserver / transputer emulator, which would have the speed performance of the existing jserver. This experimental release of the seperate 3L afserver and transputer emulator, was released as jafserver (version 0.1 beta).

August 2013 - Release of the PC based T414 Transputer emulator (jserver version 5.7). Fixed bug in the ‘in’ instruction by repositioning the CReg assignment statement before the schedule () function, to ensure CReg stored if a high priority interrupt occurs. Same bug fixed in the ‘output’ instruction. Banner update. Updated code to use LCM version 1.0.0 and its accociated DLL, in order to fix a low level LCM error seen when using multiple jserver setup on a Windows XP platform pc.

January 2013 - Release of the PC based T414 Transputer emulator (jserver version 5.6). Bug fix in update_time (). Bug fix in the 'dist' instruction. Created new function update_host_comms () to tidy up main processor loop.

December 2012 - Release of the PC based T414 Transputer emulator (jserver version 5.5). Bug fix in sp_system () in server.c. Missing externallinktype protocol definition added in processor.h. Deleted the #define Enable_Shadow_OReg option and all associated code, since not needed by real Transputer. Bug fix in ServiceNetwork IPC () and ServiceLinkInterface () to stop high priority interrupts occurring between pfix or nfix and the next instruction for a low priority task. This bug got introduced when adding the multi-processor support, but did not get spotted until large nextwork setups (5 processors) which caused illegal instruction traps to occur. Updated code to use LCM version 0.9.2 and its accociated DLL. Added additional pmonitor statements in the code to give better display and track process activity on the transputer (accessed using the /sm command line switch option). Updated comment header in SoftFloat.c to include adding of new functions (overlooked when I added them - opps!). Bug fix to overflow checking of server packet size made in server.c. Also deleted the 'if (ProcessorId == 0)' check, as redundant since check made in p.c before calling server ().

July 2012 - Release of the PC based T414 Transputer emulator (jserver version 5.4). This release corrected a bug in word (), writeword (), readbyte (), writebyte () and instructionbyte () where "case T800:" was over looked. Minor correction to /s? help banner.

July 2012 - Release of the PC based T414 Transputer emulator (jserver version 5.3). This release adds a retry mechanism on the links (in case of lost UDP packets) used by the multiprocessor support, so the order of starting the jserver's is not important. Corrected a bug in LinkXIn_handler function where strcpy wrongly used instead of memcpy. Updated a few IPC warning messages. Sorted a bug in the fpremfirst instruction to correct a floating point precision issue with the T800 emulation support. The savage benchmark now generates the same result as the real T800 (or T414 with fpu support libraries). Added a simple checksum in the packets used by the multiprocessor support. Made minor changes in the resetch instruction.

April 2012 - Release of the PC based T414 Transputer emulator (jserver version 5.2). This release removes the Wdesc register from within link interfaces and use the link channel control words only. As recently identified by Mike (see comp.sys.transputer - but this is to aid analysing only). Also added testhardchan Instruction. Removes a debug message incorrectly left in when integrating LCM. Also adds the feature in the 'in', 'out', 'outbyte' and 'outword' instructions for swapping the direction of the data sent by the Link Engine, depending on the link addresses used. See comp.sys.transputer (An underhanded programming problem.). Added multiprocessor support (i.e. multiple jservers running on single PC or networked PCs) using /sn option. Updated the Occam itools collection to run under Win 7 64bit. New .exe files added within release zip file (see 'Emulator Files' attachment).

March 2012 - Spent the last few months adding multiprocessor support (i.e. multiple jservers running on single PC or networked PCs) which is now fully working. Well it's been tested with multiple jservers running on single PC at least! Removes the Wdesc register from within link interfaces and use the link channel control words only. As recently identified by Mike (see comp.sys.transputer - but this is to aid analysing only). Added testhardchan Instruction. Added the feature in the 'in', 'out', 'outbyte' and 'outword' instructions for swapping the direction of the data sent by the link interface, depending on the link addresses used. See comp.sys.transputer (An underhanded programming problem.). A jserver beta release including all these changes is available on the 'Beta code' tab.

November 2011 - Release of the PC based T414 Transputer emulator (jserver version 5.1). Added the "start" #1FF instruction. Keeping the existing "return" support in the instruction when /sv is used (for Mike's validation support). Added link boot strapping support (i.e. peek, poke and code loading and executing) on all four external links. Started adding multiprocessor support (i.e. multiple jservers running on single PC or networked PCs). I plan to allow multiple jserver applications to communicate via their external links (using the proposed /sn number , where n for network switch enable, number is process id). I'm going to use Lightweight Communications and Marshalling (LCM) for this purpose, but I've not integrated LCM in this release. Existing host server (/sb) is fully operational (all timing unchanged from version 5.0). However the current version does not support any data in or out on the link to/from outside jserver (in next version  - I promise when LCM integrated). In the meantime, as a bonus link 2 is connected to link 3 to support debugging, so have a play. Minor changes to banner. Attempting to run jserver /sn 1 will simply hang. Its expected!

October 2011 - Release of the PC based T414 Transputer emulator (jserver version 5.0). Added full emulation of fpunoround instruction and its effects on the fpadd instruction (in particular its handling of the INT64 to REAL32 conversions). Minor changes to banner. Thanks again to Mike for his help with his fpu instruction validation tool.

August 2011 - Release of the PC based T414 Transputer emulator (jserver version 4.9). Removed all x87 fpu support and integrated SoftFloat package (written by John R. Hauser), to provides better portability and full realization using c to VHDL converter tools (such as Altium). Removed all occurrences of RetypeReal32 and RetypeReal64 function, in fpldnlsni, fpldnlsn, fpldnladdsn, fpldnlmulsn, fpldnldbi, fpldnldb, fpldnladddb and fpldnlmuldb instructions. Changes to fpusqrtlast, fpur32tor64, fpur64tor32, fpuexpdec32, fpuexpinc32, fpunoround, fpudivby2, fpumulby2, fpremfirst, fpgt, fpeq, fpstnli32, fpldnladddb, fpldnlmuldb, fpldnladdsn, fpldnlmulsn instructions. Changes made to AddIEEE, SubIEEE, MulIEEE and DivIEEE functions. The savage benchmark now produces the answer 1.1778e-09, which is only 1 lsb difference in the fraction part of the IEEE-754 answer compared with the real T800. The main bulk of the emulator development over the past couple of months has been testing of the T800 fpu instructions using the T800 validation testsuite (program written by Mike at Transputer.net). A final 'thank you' goes to Mike for his help with supplying the T800 validation testsuite and the new fpstnli32 instruction implementation.

June 2011 - Release of the PC based T414 Transputer emulator (jserver version 4.8). Bug fix in AddIEEE, SubIEEE, MulIEEE, DivIEEE and fpusqrtlast instructions to change to _PC _53 for DB. Same for fpstnli32 and fpint instructions, BUT kept fpur64tor32 using only 24bit precision (always).  Bug fix to fpur64tor32 and fpunoround instructions to add missing FTempReg.length = DB assignments. Made correction in fpu.h to the wrongly defined SN_MIN_REAL32 and DB_MIN_REAL64.  Added missing ‘if’ statement in fpstnlsn and fpstnldb instructions. Added the undocumented fpsttest instruction. Also corrected rounding mode constant definitions (in line with fpsttest instruction findings). Added new /SW command line option to display instruction warnings. Mainly added to suppress the warnings being generated by some of the standard T4xx instructions. Added warnings messages in fpu.c to monitor any instructions run with wrong SN or DB in FAReg (and FBReg). Bug fix to fpuexpinc32 and fpuexpdec32 instructions. Rewote rint function to support all four rounding modes (n, p, m and z). Added FP_RoundMode = ROUND_TO_NEAREST in fpremfirst to ensure the correct rounding method is always used, regardless of what happen in pre-seeding instruction. Made change to fpusqrtlast instruction to ensure square root of -0.0 returns -0.0. Added new rintf function (for float parameters), based on the existing rint function. Made change to fpi32tor32 instruction, to use rintf function. Got email from Mike at transputer.net and he explained that there is a bug in the Microsoft modff, since it uses a macro. I added workaround (Thanks Mike!). Using rintf in the fpint function. Minor bug fixed in fpusqrtlast instruction by adding (float) cast in front of sqrt (FAReg.sn). Updated fpuchki32 and fpuchki64 instructions. Made minor changes to fpur64tor32 and fpunoround instructions, to use .bit64 = instead of previous inaccurate float to double casting. Minor updates to fpu.h constants. Minor tidy update to fpstnli32 instruction. Finished testing all remaining fpu instruction test programs on real T800. Made change to fpi32tor32 instruction to add _controlfp () prior to casting of long to float.

May 2011 - All T800 fpu instruction test benches have been written. This has allowed me to identify a number of minor errors in the jserver emulator, which I am currently fixing. The news is there are only a few instructions which are not implemented correctly (i.e. give different test bench results compared with the real T800). One other good bit of news is that the latest beta release now runs the rayshade program, ported to run on the T800 transputer by Mike at transputer.net (see www.transputer.net/sw/sw.asp) and generates the complete wine cup image. Planned next jserver release is still aimed to be the middle of June.

May 2011 - I've spent the last couple of months (with a small holiday break in between!) writing fpu instruction test benches in Occam (with embedded ASM). It's quite a slow process but it will allow me to check if the fpu emulator support is the same as the real T800. I'm about half way through the fpu instructions. I've found a few errors so far and made changes to the beta versions of jserver. I plan to complete all the fpu instruction test benches and then release the next jserver update sometime around the middle of June.

March 2011 - Release of the PC based T414 Transputer emulator (jserver version 4.7). Added the remaining 13-off unimplemented T800 FPU instuctions. Update fpudivby2 and fpumulby2 to make more readable. Fixed bugs in fpuchki32, fpuchki64 and fpstnli32 instructions. Fixed bugs in fpadd and fpmul instructions based on Mike's comments (thanks!). Sorted handling of rounding mode in the code which switches x87 rounding mode. Fixed bugs in fpremfirst, fpldnladddb, fpldnlmuldb, fpur32tor64, fpunoround, fpgt and fgeq instructions. Added missing T800 inclusion in wsubdb instruction (in p.c).

Feburary 2011 - Release of the PC based T414 Transputer emulator (jserver version 4.6). Added T800 transputer support (/sh 800). All apart from 13 of the T800 instructions have been implemented in this release. If the unimplemented instructions are executed (nop) they display [fpu instruction]. Many thanks to Mike at transputer.net for his help in the integration of the T800 fpu code.

Feburary 2011 - I've spent the last month starting to add T800 support in the emulator. The basic shells for all instructions are now done and some FPU instructions completed. Thanks again to Mike at transputer.net for his help with basic arithmetic support.

January 2011 - Release of the PC based T414 Transputer emulator (jserver version 4.5). Added T400 transputer support. Corrected DRAM memory wrapping to fix a bug where previously higher memory addresses wrongly accesses the internal SRAM.

December 2010 - Release of the PC based T414 Transputer emulator (jserver version 4.4). Updated implementation of stnl and sb instructions (further ERB). Removed the clearing of 0x8000002C (i.e. WdescIntSaveLoc) on returning to interrupted low priority process, since not required (see comp.sys.transputer for justification). Made correction to start_process() to ensure 0x8000002C (i.e. WdescIntSaveLoc) is set to 0x80000001, when starting a high priority process after processor being either idle or at low priority. Added extra process debug pmonitor (/sm) to identify when transputer idle. Added new constants byte_select_mask and word_select_mask.

November 2010 - Release of the PC based T414 Transputer emulator (jserver version 4.3). Updated dist instruction to finally complete all CReg Transputer Extended Register Behaviour.

November 2010 - Release of the PC based T414 Transputer emulator (jserver version 4.2). Fixed bug which was causing the .btl files generated by icollect to have a few different bytes than when generated on a real transputer. The jserver now generates identical output as the real transputer running the Inmos Occam and C toolsets. Note: MUST have same transputer type and same environment variables. Included environment variable JSERVERARG support (e.g. set JSERVERARG=/sh 425). Minor changes to BreakHandler. Added Idle_p constant. Made changes to scheduler operation to not require location 0x8000002C (i.e. WdescIntSaveLoc) to be initialised at power-up. It is believed that this method is used in the real transputer. I have also streamlined the scheduler operation inline with the real transputer. Added the displaying of boot file size when using /sz, as per Inmos iserver.

November 2010 - Release of the PC based T414 Transputer emulator (jserver version 4.1). Add #1FF (start) instruction to support instruction validation used by Mike. Corrected sp.gets and sp.puts as per Inmos iserver. Minor correction to sp.flush. Made changes to server.c and p.c (enbc & disc) to support ALT construct on Link0In. Updated in, out, outbyte and outword instructions (missing writes to wp offset -3).

October 2010 - Release of the PC based T414 Transputer emulator (jserver version 4.0). This release contains some major changes and product improvements. Corrected bug in wcnt instruction. Updated xdble, xword, cword, csngl and ldiv instructions (various unsigned integer comparision problems and incorrect instruction implementations). Added power-up values for AReg and BReg. Updated implementations of fmul, rem, sb, postnormsn, mul, roundsn, unpacksn, bitrevnbits, call, wcnt and div instructions. Made changes in server.c to correct the amount of date returned by host server (now same as Inmos iserver). It was previously 8 minimum which was wrong. Added transputer validation test suite support for Mike at transputer.net. Added missing PIC in alt instruction. Improved coding flow in p.c part 2 of 2. Added simulation of 10Mbps serial link transfer time, pseudo host (PC) processing time when handling iserver sp messages between T414 and iserver (This change involved some hairy code changes!!! ) New constants added in processor.h. Improved implementations of alt, altwt, altend, talt, taltwt, enbs, diss, enbc, disc, enbt and dist instructions. Made change to update_time (), schedule () and insert () effected by the altercation changes. Updated tin instruction implementation.      A big 'thank you' to Mike at transputer.net for his help with the altercation code changes and other helpful code observations throughout beta testing.

September 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.9). Added missing Halt on Error mechanism (note: added /so to override halt on error). Corrected an overflow bug in the mul instruction. Minor code indentation corrections. Added corrections and some missing /sz debug statements (compared to Inmos iserver) in various server commands. Corrected bug in sp_error constant. Change to banner. Added new /s? for more help. Made changes to the div and rem instructions to correctly handle error conditions and CReg post instruction behaviour (based on real T414 operation - thanks again to Mike at transputer.net for his help). Added clearing of halt on error flag if a high priority process interrupts a running low priority task (a feature in the real T414).

July 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.8). Sorted a silly uninitialised variable bug (CopyFileName in main.c) which was causing a windows fault violation to occur when executing jserver with just options: /si or /si /sz or /sh 414 or /sh 425.

July 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.7). Added automatic IBOARDSIZE initialization, if not defined. In source code replaced tabs with spaces and sorted code indentation. Removed 'inline' code references. Removed duplicate core assignment. Some considerable tidying of source code. Added missing Processor Instruction Cycles (PIC) in ldnlp instruction. Added correct MemStart usage in p.c. Correction to stoperr instruction. Corrected and updated endp instruction. Removed HiTimer and LoTimer and used correct ClockReg0 and ClockReg1. Added workspace, loop end and parallel process symbolic constants in p.c. Corrected PIC in lshl and lshr instructions. Added waiting.p in tin instruction. Corrected instruction byte read. Added the remaining T425 breakpoint and debugging instructions. Corrected row variable placement in T425 block move instructions. Added StatusReg. StatusReg now emulates ErrorFlag, HaltOnErrorFlag and GotoSNPBit. StatusReg and EReg now stored in memory when a high priority interrupt of a low priority task occurs. Added missing round to nearest part of fmul instruction. Replaced interrupt variable with correctly used WdescIntSaveLoc. Deleted the TptrLoc0 and TptrLoc1 registers and mapped them correctly to use memory locations 0x80000024 and 0x80000028 (as with actual transputer). A big 'thank you' goes to Mike at transputer.net for his helpful source code review comments and suggested improvements of version 3.6 which has lead to version 3.7.

June 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.6). Mainly tidying up code prior to first release of source code. Minor bug fixes. Minor change to start-up banner. Source code made available on the website.

May 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.5). Added iserver 1024 byte block transfer (getblock and putblock) protocol support. Added CReg post instruction behaviour (source Inmos - Transputer Extended Register Behaviour) for div. Still to add fmul and dist. Increased external memory to 4Mbytes. Added DRAM wrapping (i.e. ghost memory) common when simple memory map decoding used on external memory. Fixed bug so Minix bootloader now sees the correct 4M+4K bytes of memory when run as T425 and 4M+2Kbytes of memory when run as T414.

April 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.4). Re-enabled verbose switch when /SB selected in command line. It was wrongly commented out whilst debugging another problem and I forgot to add it back. Standardized all bad icode warnings. Deleted the previously used shadow OReg register and changed the code to disable interrupts (i.e. links and timers) during the execution of Pfix and Nfix instructions within a low priority process. Added 'p' option in the ctrl-c to allow the monitoring of processes. Corrected minor bugs in some of the DEBUG messages. Corrected bug in server sp.seek command. Added extra processor cycles to account for accessing external 3 cycle multiplexed DRAM memory. Added correct processor cycle emulation for the T425 2dmove instructions (previously it was fixed at 1 cycle, now its (2p+23)*r as per datasheet).

March 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.3). Added ctrl-c support as in the Inmos iserver.

March 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.2). Added remainder of DEBUG () and INFO () message outputs as the Inmos iserver. Added the ABORT () macro to provide exit errors. The jserver.exe now returns error codes the same as the Inmos iserver. Earlier versions always returned 0.

March 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.1). Fixed a bug which caused a windows violation error. For some reason it did not show up during testing on a Windows 7 platform but did show up on Windows XP platforms (running jserver /si).

March 2010 - Release of the PC based T414 Transputer emulator (jserver version 3.0). Added CReg post instruction behaviour (source Inmos - Transputer Extended Register Behaviour) for outword, outbyte, rem and move. Still to add fmul, div, rem and dist. I've now switched my focus onto the server side of the code. I've added the /SI and /SZ options as per the real Inmos Iserver. For thoses familar with iserver source code, its the DEBUG() and INFO() message outputs.

February 2010 - Release of the PC based T414 Transputer emulator (jserver version 2.9). Fixed bugs in T425 instructions crcword and crcbyte.

February 2010 - Release of the PC based T414 Transputer emulator (jserver version 2.8). Added /SH 425 emulator support for T425 Transputer. All T425 instructions emulated except for debugger support codes (at present). Added the undocumented test instructions: testldd, teststd, testlde, testste, testlds and teststs. The actual new registers Dreg, Ereg and StatusReg are currently not used by the emulator (a job to do later!).

February 2010 - Release of the PC based T414 Transputer emulator (jserver version 2.7). Fixed another very subtle bug associated with the ALT instruction sequence. Added the remaining processor cycle timing for 'in' and 'out' instructions (all now complete!). Added CReg post instruction behaviour (source Inmos - Transputer Extended Register Behaviour) for in and out. Still to add fmul, div, rem, move, outword, outbyte and dist. Corrected bug in host server, to correctly respond to a non supported sp function request. Added correct implementation of gajw instruction (includes proc priority toggle trick if lsb of AReg =1), as per real T414/T800 silicon.

January 2010 - Release of the PC based T414 Transputer emulator (jserver version 2.6). Minor change to banner. Changed existing variable named CurPri to ProcPriority inline with transputer documentation [R4]. Corrected bug in resetch instruction. Replaced existing variables Wprt with Wdesc and created new functions to extract Wprt and ProcPriority from Wdesc. Code also changed to use 0x80000001 in Wdesc as idle state. Fixed yet another bug (which I introduced!) when adding the high priority interrupt mechanism. Found two more very subtle bugs associated with the high priority interrupt mechanism (Hopefully now all fixed!). As a result idebug.btl runs on the emulator and displays the start-up banner.

December 2009 - Release of the PC based T414 Transputer emulator (jserver version 2.5). Finished adding real instruction cycle timing and high and low timer processing to correctly emulate a 20MHz T414 device. All done, except in and out instructions which still are fixed at 18 cycles (instead of 20 or 2w+18). Various other minor bug fixes and feature improvements (in particular fix to sp_pollkey to fix isim problem). Started adding CReg post instruction behaviour (source Inmos - Transputer Extended Register Behaviour) - have added lmul, ldiv, lshl, lshr, sb and lend. Still to add fmul, div, rem, move, in, out, outword, outbyte and dist.

December 2009 - Release of the PC based T414 Transputer emulator (jserver version 2.4). Added real instruction cycle timing and high and low timer processing to correctly emulate a 20MHz T414 device. Various other minor bug fixes and feature improvements whilst trying to get Minix OS to run. The high priority interrupt mechanism is now fully working.

October 2009 - Release of the PC based T414 Transputer emulator (jserver version 2.3). Corrected memory size to reflect the T414 2K internal memory plus 2Mbyte external memory.

September 2009 - Release of the PC based T414 Transputer emulator (jserver version 2.2). Corrected a memory accessing bug if trying to read or write outside the external 2Mbyte memory address space.

September 2009 - Release of the PC based T414 Transputer emulator (jserver version 2.1). Corrected a bug associated with command line arguments, which has previously meant that some switch order combinations did not work. Now fixed!

August 2009 - Release of the PC based T414 Transputer emulator (jserver version 2.0). Command line arguments can now be entered in both upper and lower case (or combination).

June 2009 - Release of the PC based T414 Transputer emulator (jserver version 1.9). I've spent the last two years on and off debugging the software and now I'm happy with the basic emulation behaviour and the operation of the Inmos Occam Toolset running on the emulator. To celebrate, I've setup this website for anyone intrested in having a play with a 20 year old parallel relic! (which was years ahead of its time).

November 2006 - Downloaded the source code from Julian Highfield's website. Compiled it for Win32 command console (after some minor code tweaks) and then started debugging to get it running various btl files and the Occam and C Inmos toolset.