Publications

Google Citations

Refereed Journal Papers

• 1. N. Mohan, M. Sachdev, "Low-Leakage Storage Cells for Ternary Content Addressable Memories," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 5, pp. 604-612, May 2009.

  2. N. Mohan, W. Fung, D. Wright, M. Sachdev, "A Low-Power Ternary CAM with Positive-Feedback Match Line Sense Amplifiers," IEEE Transactions on Circuits and Systems I (TCAS-I): Regular Papers, vol. 56, no. 3, pp. 566-573, Mar. 2009.

  3. N. Mohan, M. Sachdev, "Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs," IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 9, pp. 2054-2060, Sep. 2007.

  4. N. Mohan, W. Fung, D. Wright, M. Sachdev, "Design techniques and test methodology for low-power TCAMs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 6, pp. 573- 586, Jun. 2006.

  5. N. Mohan, K. S. Karim, A. Nathan, "Design of Multiplexer in Amorphous Silicon Technology," Journal of Vacuum Science and Technology A, Vol. 20, No. 3, pp. 1043-1047, May 2002.

Refereed Conference Papers

• 1. N. Mohan, W. Fung, D. Wright, M. Sachdev, "Match line sense amplifiers with positive feedback for low-power content addressable memories," Proceedings of the IEEE Custom Integrated Circuits Conference (CICC 2006), San Jose, pp. 297-300, Sep. 10-13, 2006.

  2. N. Mohan, M. Sachdev, "Novel ternary storage cells and techniques for leakage reduction in ternary CAM," Proceedings of the IEEE International SOC Conference (SOCC 2006), Austin, Texas, pp. 311-314, Sep. 24-27, 2006.

  3. N. Mohan, W. Fung, M. Sachdev, "Low-power priority encoder and multiple match detection circuit for ternary content addressable memory," Proceedings of the IEEE International SOC Conference (SOCC 2006), Austin, Texas, pp. 253-256, Sep. 24-27, 2006.

  4. N. Mohan, M. Sachdev, "A Comparative Study of Low-Power Techniques for Ternary CAMs," Proceedings of the IEEE International Conference for Upcoming Engineers (ICUE 2006), Waterloo, Ontario, Canada, May 13-14, 2006.

  5. N. Mohan, M. Sachdev, "Low Power Dual Matchline Ternary Content Addressable Memory," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, pp. 633-636, May 23-26, 2004.

  6. N. Mohan, M. Sachdev, "A Static Power Reduction Technique for Ternary Content Addressable Memories," Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2004), Niagara Falls, pp. 711-714, May 2-5, 2004.

  7. N. Mohan, K. S. Karim, S. Prakash, A. Nathan, "Stability Issues in Digital Circuits in Amorphous Silicon Technology," Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2001), Toronto, pp. 583-588, May 13-16, 2001.

  8. K. S. Karim, P. Servati, N. Mohan, A. Nathan, J.A. Rowlands, "VHDL-AMS Modeling and Simulation of a Passive Pixel Sensor in a-Si:H Technology for Medical Imaging," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australia, Volume 5, pp. 479-482, May 6-9, 2001.

Miscellaneous Articles

• 1. N. Mohan, A. Kumar, "Modeling ESD protection," IEEE Potentials, pp. 21-24, Feb-Mar 2005.

  2. N. Mohan, "Efficient Testing of Analog and Mixed Signal ICs using Verilog-A," Third Annual OSEE, EE Times, Nov. 13, 2002.