Chip Gallery

A low-noise, low-power neural signal acquisition analog front-end IC for implantable medical devices

• 칩 주요 특징/Features: A low-noise low power analog front-end IC for neural signal recording. Achieved max. 40 dB gain, 3.39 uVrms integrated input referred noise over 1Hz-6.5 kHz, NEF of 1.93, supports up to 280 mVpp CM mode artifact, 60 mVpp DM mode artifact, consuming 1.49 uW @ 1-V 

• 설계블록/Blocks: neural recording amplifier with modified folded-cascode OTA, programmable gain amplifier with tunable filter, buffer

• 사용 반도체 공정/Process: DBHitek 0.18um BCD process

• 칩 면적/Core area: 0.21 mm²

• 설계자/Designer: D. Choi

• Work published in IEIE J. of Semiconductor Technology and Science 2022

A 15-V high-voltage generation charge pump IC for neural implant devices (neural stimulation)

• 칩 주요 특징/Features: A high-voltage generation charge pump IC with input voltage modulated regulation, generates 15 V output from 3.2 V input at 5 mA load current with over 88% power conversion efficiency

• 설계블록/Blocks: charge pump, regulation circuits

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.98 mm²

• 설계자/Designer: G. Paksi

• Work published in IEIE Trans. Smart Processing and Computing 2022

A neural stimulator IC with chopped pulse modulation based active charge balancing

• 칩 주요 특징/Features: Current mode neural stimulator with a simple and effective active charge balancer, automatic electrode shorting functionality, can deliver up to 1 mA of stimulation current with 12.3 V voltage compliance, all implemented using standard CMOS process. Less than 3 mV residual potential after charge balancing. 

• 설계블록/Blocks: output driver, DAC, level-shifters, active charge balancer

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.09 mm²

• 설계자/Designer: J.-Y. Son

• Work published in IEIE J. of Semiconductor Technology and Science 2021

A four-channel, low-noise, low-power neural signal acquisition analog front-end IC for implantable medical devices

• 칩 주요 특징/Features: A low-noise low power analog front-end IC for neural signal recording. Achieved max. 63 dB gain, 3.16 uVrms integrated input referred noise over 10 kHz, NEF of 2.04, consuming 2.82 uW @ 1-V 

• 설계블록/Blocks: neural recording amplifier with inverter-stacked OTA, programmable gain amplifier with tunable filter, Buffer, mux, ADC driver, SAR ADC (not included in the journal content)

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.21 mm²

• 설계자/Designer: L. Tran (ADC designed by N. Nguyen)

• Work published in Elsevier Microelectronics Journal 2021

A neural stimulator IC with anodic current pulse modulation based active charge balancing

• 칩 주요 특징/Features: Current mode neural stimulator with a simple and effective active charge balancer, optional electrode shorting functionality, can deliver up to 1 mA of stimulation current with 12.3 V voltage compliance, all implemented using standard CMOS process. Less than 22 mV residual potential after charge balancing.   

• 설계블록/Blocks: output driver, DAC, level-shifters, active charge balancer

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.11 mm²

• 설계자/Designer: J.-Y. Son

• Work published in IEEE Access 2020

A high-voltage generation charge pump IC with input voltage modulated regulation for neural implant devices (neural stimulation)

• 칩 주요 특징/Features: A high-voltage generation charge pump IC with novel input voltage modulated regulation, generates 12.8 V output from 2.8 V input at 1 mA load current with over 80% power conversion efficiency

• 설계블록/Blocks: charge pump, regulation circuits

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.6 mm²

• 설계자/Designer: A. Abdi

• Work published in IEEE Trans. Circuits and Systems II 2019

A highly-integrated ultra-low-power receiver RF Front-End IC for Medical Implant Communications Service (MICS) biomedical telemetry

• 칩 주요 특징/Features: Sub-500 uW @ 1-V ultra-low-power 402-405 MHz operation with AC-coupled current mirroring amplifier

• 설계블록/Blocks: low-noise transconductor, AC-coupled current mirror amplifier, mixer, LO buffer, peripheral bias circuits

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.29 mm²

• 설계자/Designer: H.-K. Cha

• Work published in Journal of Circuits, Systems, and Computers 2019

A low-noise, low-power neural recording analog front-end IC for implantable medical devices

• 칩 주요 특징/Features: A low-noise low-power analog front-end IC for neural signal recording. Achieved max. 61 dB gain, 4.74 uVrms integrated input referred noise over 10 kHz, NEF of 2.91, consuming 2.28 uW @ 1-V 

• 설계블록/Blocks: low-noise neural recording amplifier with current-reuse complementary cascoded OTA, programmable gain amplifier with tunable filter

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.16 mm²

• 설계자/Designer: H. S. Kim

• Work published in IEIE Journal of Semiconductor Technology and Science 2018

A capacitor-less high PSRR LDO regulator for implantable medical devices

• 칩 주요 특징/Features: A capacitor-less PSRR low dropout (LDO) regulator with 1.2 V input and 1 V output and regulates at 1-mA load current 

• 설계블록/Blocks: LDO regulator 

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.075 mm²

• 설계자/Designer: M. G. Song

• Work presented at ITC-CSCC 2018

A low-noise, low-power neural recording amplifier IC using two-stage OTA for implantable medical devices

• 칩 주요 특징/Features: An AC-coupled capacitive-feedback neural recording amplifier employing two-stage OTA with modified current buffer compensation 

• 설계블록/Blocks: low-noise neural recording amplifier, drive buffer

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.09 mm²

• 설계자/Designer: H. S. Kim

• Work published in Journal of Circuits, Systems, and Computers 2018

A bidirectional neural interface analog front-end IC with embedded isolation switch for medical implant devices

• 칩 주요 특징/Features: A biphasic current mode neural stimulator with embedded isolation switch, generates up to 1 mA stimulation current, voltage compliance of over 11 V. A low-voltage low-power current-mirror OTA-based AC-coupled capacitive-feedback neural recording amplifier. All the circuits implemented and integrated together using 0.18um standard CMOS process.  

• 설계블록/Blocks: neural stimulator, neural recording amplifier.

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.29 mm²

• 설계자/Designer: A. Abdi

• Work published in Elsevier Microelectronics Journal 2016

A highly-integrated bidirectional ultrasound interface analog front-end IC with reconfigurable pulser/switch for medical imaging applications

• 칩 주요 특징/Features: A reconfigurable pulser/switch for minimized die area. over 65% reduction in area in comparison to previous work

• 설계블록/Blocks: reconfigurable pulser/switch, preamplifier, 16-channel ver.

• 사용 반도체 공정/Process: Sk Hynix/Magnachip 0.18um CMOS process

• 칩 면적/Core area: 0.052 mm²

• 설계자/Designer: H.-K. Cha

• Work published in IET Electronics Letters 2015

Bidirectional ultrasound interface analog front-end IC for medical imaging systems

• 칩 주요 특징/Features: Integrated 15-V bidirectional analog front-end IC for ultrasound applications using low-voltage standard CMOS process (for CMUT interface)

• 설계블록/Blocks: pulser, isolation switch, preamplifier

• 사용 반도체 공정/Process: TSMC 0.18um CMOS process

• 칩 면적/Core area: 0.15 mm²

• 설계자/Designer: A. Banuaji

• Work published in IEEE Trans. Circuits and Systems II 2014

High-voltage transmitter IC for ultrasound medical imaging using stacked dynamically biased CMOS transistors

• 칩 주요 특징/Features: over 10V operation using stacked CMOS transistors

• 설계블록/Blocks: output driver, level-shifters (for CMUT interface)

• 사용 반도체 공정/Process: Global Foundry 30-V 0.18um BCD (Bipolar, CMOS, DMOS) process

• 칩 면적/Core area: 0.022 mm²

• 설계자/Designer: H.-K. Cha

• Work published in IEEE Trans. Circuits and Systems II 2013

Wireless power receiver and data transmission IC for neural recording applications

• 칩 주요 특징/Features: Wireless power receiver and data transmitter for neural recording

• 설계블록/Blocks: rectifier, LDO, wireless transmitter, digital baseband

• 사용 반도체 공정/Process: Global Foundry 0.18um CMOS process

• 설계자/Designer: K.-W. Cheng (IME), H.-K. Cha et. al

• Work presented at IEEE Asian Solid-State Circuits Conf. 2012

Flow sensor IC for implantable biomedical applications

• 칩 주요 특징/Features: Wirelessly powered implant device for blood flow monitoring

• 설계블록/Blocks: rectifier, ADC, LDO, sensor interface 

• 사용 반도체 공정/Process: Global Foundry 0.18um CMOS process

• 설계자/Designer: J.H. Cheong (IME), H.-K. Cha et. al

• Work presented at IEEE Asian Solid-State Circuits Conf. 2012

High-efficiency single-input dual-output AC-DC converter IC for wireless power transfer in implantable biomedical applications

• 칩 주요 특징/Features: 79.5% power conversion efficiency at 13.56 MHz, single-input dual-output AC-DC converter with comparator-based rectifiers

• 설계블록/Blocks: rectifiers, comparator

• 사용 반도체 공정/Process: Global Foundry 0.18um CMOS process

• 칩 면적/Core area: 0.18 mm²

• 설계자/Designer: H.-K. Cha

• Work published in Elsevier Microelectronics Journal 2014

High efficiency rectifier IC for wireless power transfer in implantable biomedical applications

• 칩 주요 특징/Features: 70% power conversion efficiency at 13.56 MHz, 3-stage differential-drive rectifier with low input voltage operation

• 사용 반도체 공정/Process: Global Foundry 0.18um CMOS process

• 칩 면적/Core area: 0.125 mm²

• 설계자/Designer: H.-K. Cha

• Work published in Journal of IEIE 2013

High efficiency rectifier IC for wireless power transfer in implantable biomedical applications

• 칩 주요 특징/Features: 81.9% power conversion efficiency at 13.56 MHz using comparator-based switching

• 설계블록/Blocks: rectifier, comparator

• 사용 반도체 공정/Process: Global Foundry 0.18um CMOS process

• 칩 면적/Core area: 0.009 mm²

• 설계자/Designer: H.-K. Cha

• Work published in IEEE Trans. Circuits and Systems II 2012

Ultra-low-power low-voltage low-IF wireless receiver IC for MedRadio biomedical telemetry

• 칩 주요 특징/Features: 1.2 mW @ 1-V 401-406 MHz operation with multi-channel support.

• 설계블록/Blocks: LNA, mixer, frequency synthesizer with quadrature VCO, complex bandpass filter, limiter, RSSI, peripheral bias circuits

• 사용 반도체 공정/Process: Global Foundry 0.18um CMOS process

• 칩 면적/Core area: 1.8 mm²

• 설계자/Designer: H.-K. Cha et. al

• Work published in Microw. Optical Tech. Letters 2012

Ultra-low-power low-voltage RF Front-End IC in low-IF wireless receiver for MedRadio biomedical telemetry

• 칩 주요 특징/Features: Sub-500 uW @ 1-V ultra-low-power 401-406 MHz operation with novel current reuse complementary LNA

• 설계블록/Blocks: LNA, mixer, passive polyphase filter, LO buffer, peripheral bias circuits

• 사용 반도체 공정/Process: Global Foundry 0.18um CMOS process

• 칩 면적/Core area: 0.7 mm²

• 설계자/Designer: H.-K. Cha

• Work presented at IEEE Asian Solid-State Circuits Conf. 2010 and published in IEEE Trans. Microw. Theory and Tech. 2011

Low-power Wideband RF Front-End IC in direct conversion receiver for Digital TV tuner applications 

• 칩 주요 특징/Features: 48-860 MHz operation with 60 dB HRR for all harmonics

• 설계블록/Blocks: Wideband LNA, 48-180 MHz tunable passive LC filter, harmonic rejection mixer with calibration, divider and LO buffer, peripheral bias circuits, I2C

• 사용 반도체 공정/Process: TSMC 0.18um CMOS process

• 칩 면적/Die area: 3.1 mm x 2.9 mm (incl. pads)

• 설계자/Designer: H.-K. Cha et. al

• Work published in IEEE Trans. Microw. Theory and Tech. 2010

RF Programmable Gain Amplifier in dual-conversion receiver for Digital TV tuner applications 

• 칩 주요 특징/Features: 1.22 GHz operation with current amplification for good linearity performance

• 사용 반도체 공정/Process: TSMC 0.18um CMOS process

• 칩 면적/Core area: 0.62 mm²

• 설계자/Designer: H.-K. Cha

• Work published in IEICE Trans. Electronics 2010

Wideband Low-Noise Amplifier for Digital TV tuner applications 

• 칩 주요 특징/Features: 48-860 MHz operation with noise canceling and MGTR technique for good NF/linearity performance

• 사용 반도체 공정/Process: TSMC 0.18um CMOS process

• 칩 면적/Core area: 0.21 mm²

• 설계자/Designer: H.-K. Cha

• Work published in IEICE Trans. Electronics 2010

Wideband RF Front-End IC in direct conversion receiver for Digital TV tuner applications 

• 칩 주요 특징/Features: 48-860 MHz operation with calibrated harmonic rejection mixer with over 70 dB 3rd-order HRR

• 설계블록/Blocks: Wideband LNA, harmonic rejection mixer with calibration, divider and LO buffer

• 사용 반도체 공정/Process: TSMC 0.18um CMOS process

• 칩 면적/Core area: 2 mm²

• 설계자/Designer: H.-K. Cha

• Work published in IEEE Microw. Wireless Comp. Letters 2008

32-kB OTP ROM embedded in a 16-b microcontroller

• 칩 주요 특징/Features: High density OTP ROM using standard CMOS process

• 설계블록/Blocks: 32-kB OTP ROM, SRAM, MCU, peripheral digital logic

• 사용 반도체 공정/Process: TSMC 0.18um CMOS process

• 칩 면적/Die area: 3.3 mm x 3.0 mm (incl. pads)

• 설계자/Designer: H.-K. Cha et. al

• Work published in IEEE J. of Solid-State Circuits 2006