Lab 1: Number Sequencing Computer

This lab covers some basic concepts in computer architecture by creation of a Number Sequencing Computer (NSC), which is a stored program machine that displays a number sequence. This write-up covers the NSC implementation compatible with Quartus 10.1 or higher. The student is expected to have Quartus already installed. This write-up also assumes the reader is already familiar with the basic operation of the NSC from the class lecture.

The tasks in this lab are:

• Unzip the NSC archive and verify that you can simulate the design with no modifications in Quartus. WARNING: Do not unzip the NSC archive file into any directory whose directory components have spaces in them (i.e., C:\Users\John C. Smith\.... ) or else the Quartus simulation may fail. The safest place to put it is in C:\ece3724.

• Modify the contents of the read only memory (ROM) to output a 7-digit number of your choice.

• Modify the NSC design to accommodate a program that can contain up to 32 instructions.

As always, read through the entire lab and scan the supplied files before starting to work.

If you have not installed Intel Quartus and Modelsim, visit the Lab 0 page to download them.

Pre-lab (20 points)

Follow along with the video tutorial and complete the pre-lab checkoff requirements below before you enter the lab. Note that Quartus and ModelSim should already be installed on your computer and tested. If you experience technical difficulties, notify a TA well before the lab begins so these issues can be resolved ahead of time. Waiting until lab time to discover that your software has become inoperational or that you cannot view the video means that you will forfeit your pre-lab points. Please see the lab policy summary for further details. 

Tutorial Video

The tutorial video walks you through the prelab, (which is also Task 1 and the first part of Task 2). The video, while still relevant, is from 2011, and uses slightly older software. Note the following:

• 0:00 - Put the nsc_altera folder in C:\ece3724. This should have been done during Lab 0. 

• 0:46 - Still do not put spaces in your filenames.

• 1:28 - Use Quartus 17.1 Prime Lite. It includes ModelSim.

• 3:11 - Switch between Hierarchy and Files with dropdown menu, not tabs.

• 3:40 -Close the IP Catalog window on the right side of the screen to give yourself more room.

• 3:46 - View -> Fit in Window (Ctrl-Alt-W)

• 4:08 - Chapter 2 Slides (on Canvas)

• 8:59 - Zoom Full (filled in magnifying glass icon) is now located on the LEFT side of the menu buttons. You can also press F. 

• 9:00 - You can zoom in by pressing I, and zoom out by pressing O. You can also close the "sim - Default" and "Objects" windows to see even better. If you close the entire ModelSim window by mistake you can get it back by recompiling, or, if you haven't made any changes, by Tools->Run Simulation Tool->Gate-Level Simulation.

• 12:26 - If you've edited lines 30-36 of myrom.v (and the comments!) to change the output to your own phone number, then you've already finished Task 1.  

• 16:00 - Compilation shortcut: Ctrl-L

• 17:23 - You have completed the pre-lab. However as Dr. Jones says in the video, it is highly encouraged to keep working on your own past this point before you come to lab.

Checkoff:

• • Code and comments in myrom.v modified with your own number (10 points).

  • Address bus in nsc.bdf widened to 5 bits (10 points).

(Note: There is nothing to hand in for this or any pre-lab. The TA checks it off at the beginning of lab.)

Task 1: Modify the NSC to display your number (20 points)

Open the myrom.v file within Quartus. Edit the Verilog code in the case statement to alter the contents of the ROM so that it contains a program that displays your 7-digit phone number. You should also alter the comments to reflect your code changes: If you change a digit from 0011 to 0111, the comment next to it should say "3" not "7". Save your file after the edits are finished, recompile the design, and re-simulate. Verify that the displayed number is now your 7-digit phone number. 

Checkoff: Show a TA the ModelSim simulation displaying your phone number. If there's no TA around (i.e. you're doing the lab at home) and you're already on Task 2, you'll get the checkoff for Task 1 as long as you show that you've edited myrom.v with your own number.

Task 2: Modify the NSC to support 32 locations (40 points)

Expanding the NSC design to support 32 memory locations requires several changes. 

Modification of myrom.v

Double left click on myrom.v to open the text editor on the Verilog file.

• The address bus must be increased in width from 4 bits to 5 bits; change the statement “input [3:0] addr” to “input [4:0] addr”.

• The data bus must be increased from 6 bits to 7 bits since the address field in the instruction has increased by one bit. Change the statement “output [5:0] dout” to “output [6:0] dout”. Also change the statement “reg [5:0] dout” to “reg [6:0] dout”. Remember to update the schematic.

• Modify the case statement to cover all 32 cases for the ROM locations: Make your current program begin at location 16 instead of 0. Now add a new line at the top - at location 0, add a jump instruction (not a jump conditional) that jumps to location 16. At the end of the program, jump back to location 16 instead of 0. WARNING: The memory width has been increased from 5 bits to 6 bits, so all memory values now require an extra bit! Be careful where you add it! HINT: Do not add 16 new lines of code. 

Once the edits to myrom.v are finished, save the file and create/update the symbol in nsc.bdf as shown in the video. 

Modification of mycounter.v

The counter has to be changed from a 4-bit counter to a 5-bit counter.

• Change the statement “input [3:0] d” to “input [4:0] d” (width is now 5 bits).

• Change the statement “output [3:0] q” to “output [4:0] q” (width is now 5 bits).

• Change the statement “reg [3:0] q” to “reg [4:0] q” (width is now 5 bits).

• Change the statement “if (!r) q <= 'b0000” to “if (!r) q <= 'b00000” (reset value is now 5 bits).

Verify that the file analyzes without any errors (Processing -> Analyze Current File), then re-create the symbol for this component as you did for myrom.v and update the symbol on the schematic.

Modification of nsc.vt

You will need to edit the test bench in the file nsc.vt (Verilog testbench file) to change its width from 4 bits to 5 bits. This will allow you to see the entire 5 bit address within ModelSim.  

Other modifications

• You'll need to perform the remaining modifications on your own. Look at your schematic to make sure the NSC can now accomodate memory addresses of 5 bits.

• You'll have to modify the output register as well, following a similiar procedure as with the ROM and the counter. 

• You also need to adjust the control logic. HINT: Which bits of the instruction represent the opcode?

Resimulate the design and verify that your program is executing from locations in the top half of the memory (memory locations 16 to 31) and that the correct number sequence is displayed. Make certain that your addresses 0-31 are written in decimal in the simulation - if necessary, right-click on the variable name and change the radix.

Checkoff: Show the TA your ModelSim simulation performing properly. It should look like the following, except with your number, not Jenny's:

Tips

• In nsc.bdf, you do not have to delete or add any components or connections; all you have to do is rename existing nets. For example, the bus that is connected to the q[4..0] port of mycounter.v must be renamed from addr[3..0] to addr[4..0]. 

• If doubleclicking labels like in the video is frustrating, right-click and go to "Properties" as shown below:

• You can put underscores in Verilog numbers to make them easier to read, for example separating the opcode and operand like this:

• See the troubleshooting page for more help.

Report

See Lab Policy Summary for formatting guidance and a sample brief report.

1. Include the source code of myrom.v as an attachment to your Lab 1 submission - the actual file, not a screenshot. Replace the meaningless automated file header with your own, like so:

Just like in the original program, next to each line of machine code (the binary) should be a comment containing the correct line number and assembly code that accurately states what the machine code does.

2. Include a screenshot of your schematic (nsc.bdf) for Task 2. Make it large enough to be legible and crop unnecessary portions of the Quartus screen.

3. Briefly discuss the changes made to the number sequencing computer for Task 2 and the reasoning behind the changes.

4.  Assume a new instruction is needed called 'INC' that will increment the current value in the OUTPUT register. What changes are required to the decode logic and overall design to implement this? Show a sketch or rough schematic of the necessary modifications. There is more than one correct solution.