Taegun Yim
Curriculum Vitae
CONTACT INFORMATION
Department of Electrical and Electronic Engineering ytg321@yonsei.ac.kr
3rd Eng. building LinkedIn
Yonsei University
50 Yonsei-ro
Seodaemun-gu, Seoul 03722, Korea
EDUCATION
• Yonsei University, Seoul, Republic of Korea
Ph. D. of Electrical and Electronic Engineering, March 2019 to August 2026
Advisor: Prof. Hongil Yoon
• Yonsei University, Seoul, Republic of Korea
Master of Electrical and Electronic Engineering, March 2017 to February 2019
Advisor: Prof. Hongil Yoon
• Hankuk University of Foreign Studies (HUFS), Yong-in, Republic of Korea
Bachelor of Electronic Engineering, March 2009 to February 2017
Advisor: Prof. Junwoo Kang
EXPERIENCE
• Research Assistant, March 2017 to August 2026
Integrated Devices and Circuits Laboratory (IDC lab), Yonsei University, Seoul, Republic of Korea
- Established first analog ASIC multi-project wafer (MPW) setup and tape-out infrastructure in the research lab, including successfully approved proposal, PDK integration, design environment setup, and workflow coordination.
- Experienced in Samsung 28 nm Low Power Plus, DBHitek 180 nm, and NCSU 45 nm processes.
- Developed and validated full analog ASIC designs using Cadence Virtuoso and HSPICE.
RESEARCH INTEREST
• Analog Circuits for Low-Voltage Systems
• Low-Power & High-Efficiency Integrated Circuits for Power Management ICs
- Charge pump circuits (VPP, VBB generators)
- Voltage reference circuit
• Time-Domain Analog-to-Digital Converter (TD-ADC)
- Time-to-Digital Converter (TDC) circuit
• Advanced Semiconductor Memory
- DRAM, STT-MRAM sense amplifiers
- Flip-flops
TECHNICAL SKILLS
• Programming Languages: C, Python
• Hardware Description Language: Verilog
• EDA Tools: Cadence Virtuoso, HSPICE, PSpice, LTspice, ModelSim
AWARDS AND HONORS
• Samsung Electronics Strategic Academia-Industry Collaboration Outstanding Patent Award
- Grand Prize, 2024
- Selected by DRAM Design Team, Memory Division, Samsung Electronics
- Primary inventor alongside Prof. Hongil Yoon; prize officially awarded to Prof. Hongil Yoon.
• Best Paper Award
- Korea Test Conference (KTC), 2018
- 1st author
PUBLICATIONS
JOURNAL PUBLICATIONS (First Author: 3, Co-Author: 1)
4. Taegun Yim and Hongil Yoon, “A Separated Pre-charge Sense Amplifier with Fast-Sensing, Low-Power, Small-Area, and High-Reliability for Hybrid MTJ/CMOS Logic Circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 6, pp. 3953-3961, Jun. 2026.
3. Taegun Yim and Hongil Yoon, “Single-Ended Back-Bias Voltage (VBB) Generator Using One Pumping Capacitor,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 9, pp. 554-558, Apr. 2025.
2. Taegun Yim, Choongkeun Lee, and Hongil Yoon, “High Speed Back-Bias Voltage (VBB) Generator with Improved Pumping Current,” Electronics, Special issue: Low-Voltage Integrated Circuits Design and Applications, vol. 9, no. 11, pp 1835-1844, Nov. 2020.
1. Choongkeun Lee, Taegun Yim, and Hongil Yoon, “A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM,” Electronics, Special issue: Low-Voltage Integrated Circuits Design and Applications, vol. 9, no. 11, pp 1769-1779, Oct. 2020.
CONFERENCE PUBLICATIONS (INTERNATIONAL) (First Author: 2, Co-Author: 7)
9. Suna Lee, Taegun Yim, Choongkeun Lee, and Hongil Yoon, “A Compact Low-Voltage and Low-Power Flip-Flop with Static, Contention-Free, and Redundant-Transitions-Free Operation,” IEEE International Symposium on Circuits and Systems (ISCAS) May, 2026. (2026-05-24)
8. Geonwoo Kim, Minho Seo, Jaeyeong Ha, Taegun Yim, and Hongil Yoon, “A Precision Bandgap Reference with 0.8 ppm/ºC TC for Wide-Temperature SoC Applications,” International SoC Design Conference (ISOCC) Oct, 2025. (2025-10-17)
7. Hyeongjun Kim, Taegun Yim, Choongkeun Lee, and Hongil Yoon, “A picowatt CMOS voltage reference with 0.046 %/V line sensitivity for a low power IoT system,” International SoC Design Conference (ISOCC) Oct, 2023. (2023-10-26)
6. Taegun Yim, Choongkeun Lee, and Hongil Yoon, “A High Speed Modified Dickson Charge Pump,” IEEE International Symposium on Circuits and Systems (ISCAS) May, 2021. (2021-05-24)
5. Choongkeun Lee, Taegun Yim, and Hongil Yoon, “Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM,” IEEE TENCON November, 2018. (2018-10-30)
4. Seungjin Lee, Taegun Yim, and Hongil Yoon, “Low-Energy Consumption Write Circuit Using Comparing Operation in STT-MRAM,” IEEE TENCON November, 2018. (2018-10-30)
3. Taegun Yim, Seungjin Lee, Choongkeun Lee, and Hongil Yoon, “A Low-Voltage Charge Pump with High Pumping Efficiency,” IEEE TENCON November, 2018. (2018-10-31)
2. Kyungseon Cho, Seungjin Lee, Choongkeun Lee, Taegun Yim, and Hongil Yoon, “Low Power Multi-Context Look-Up Table (LUT) Using Spin-Torque Transfer Magnetic RAM for Non Volatile FPGA,” International SoC Design Conference (ISOCC) Nov, 2017. (2017-11-07)
1. Seungjin Lee, Kyungseon Cho, Choongkeun Lee, Taegun Yim, and Hongil Yoon, “Energy-Efficient Write Circuit in STT-MRAM Based Look-Up Table (LUT) Using Comparison Write Scheme,” International SoC Design Conference (ISOCC) Nov, 2017. (2017-11-07)
CONFERENCE PUBLICATIONS (DOMESTIC) (First Author: 5, Co-Author: 3)
8. Xingzhi Xu, Choongkeun Lee, Taegun Yim, Suna Lee, and Hongil Yoon, “A Pulsed Flip-Flop Circuit using Shunt Capacitor Technique for Vernier Time-to-Digital Converter,” Korea Test Conference, July, 2024. (2024-07-02)
7. Taegun Yim, Choongkeun Lee, Xingzhi Xu, Suna Lee, and Hongil Yoon, “An Inverted Input Vernier Delay Line for An Efficient Time-to-Digital Converter,” Korea Test Conference, June, 2023. (2023-06-27)
6. Taegun Yim, Choongkeun Lee, and Hongil Yoon, “A Time-to-Digital Converter using Sense Amplifier Based Flip-Flop with High Speed Output for Built-Off Self-Test,” Korea Test Conference, October, 2020. (2020-10-15)
5. Kyunghwan Kim, Choongkeun Lee, Taegun Yim, Youngchan Yoon, and Hongil Yoon, “New Test Methodology for Detecting Reliability Failure,” Korea Test Conference, June, 2019. (2019-06-25)
4. Taegun Yim, Choongkeun Lee, Kyunghwan Kim, Youngchan Yoon, and Hongil Yoon, “An Efficient Skew Measurement Method using Vernier Delay Line with Less Area Buffer for Built-Off Self-Test,” Korea Test Conference,” Korea Test Conference, June, 2019. (2019-06-25)
3. Chanho Park, Taegun Yim, Choongkeun Lee, and Hongil Yoon, “A Design of Compact Vernier Delay Line using Flip-Flop Sharing,” Korea Test Conference, June, 2018. (2018-06-26)
2. Taegun Yim, Chanho Park, Choongkeun Lee, and Hongil Yoon, “A Skew Measurement Method using An Effective Vernier Delay Line Design for Built-Off Self-Test,” Korea Test Conference, June, 2018. (2018-06-26)
1. Taegun Yim, Choongkeun Lee, and Hongil Yoon, “A Skew Measurement Method using A New Vernier Delay Line Design for Built-Off Self-Test,” Korea Test Conference, June, 2017. (2017-06-27)
PATENTS (OVERSEA)
2. Hongil Yoon and Taegun Yim, “NEGATIVE VOLTAGE GENERATOR AND MEMORY DEVICE INCLUDING THE SAME,” Application 202510655013.0 2025/05/21 China.
1. Hongil Yoon and Taegun Yim, “NEGATIVE VOLTAGE GENERATOR AND MEMORY DEVICE INCLUDING THE SAME,” Application 19/082,970 2025/03/18 US.
PATENTS (DOMESTIC)
5. Hongil Yoon and Taegun Yim, “NEGATIVE VOLTAGE GENERATOR AND MEMORY DEVICE INCLUDING THE SAME,” Application 10-2024-0080290 2024/06/20 Republic of Korea.
4. Hongil Yoon and Taegun Yim, “HIGH SPEED CHARGE PUMP CIRCUIT,” Grant 10-2583915 2023/10/10 Republic of Korea.
3. Hongil Yoon and Taegun Yim, “TIME-TO-DIGITAL CONVERTER USING SENSE AMPLIFIER BASED FLIP-FLOP WITH HIGH SPEED OUTPUT FOR BUILT-OFF SELF-TEST,” Grant 10-2446422 2022/09/19 Republic of Korea.
2. Hongil Yoon and Taegun Yim, “Efficient Skew Measurement Apparatus Using Vernier Delay Line for BOST with Low Area Buffer,” Grant 10-2205126 2021/01/14 Republic of Korea.
1. Hongil Yoon and Taegun Yim, “Built Off Self-Test Circuit Apparatus and Time to Digital Converter with New Vernier Delay Line Design,” Grant 10-1957412 2019/3/6 Republic of Korea.
TEACHING EXPERIENCE
• Undergraduate Courses
- Engineering Information Processing: Led weekly lab sessions on C programming (2017F, 2018F, 2019F, 2020F, 2021F, 2022F, 2024F, 2025F)
- Digital Logic Circuit: Held office hours and graded homework (2019S, 2020S, 2023S)
- Digital Microelectronics: Held office hours, graded homework, and assisted in lab sessions (2023F)
- Electrical/Electronic Application Experiment: Led weekly labs on HDL and FPGA (2017F)
- Electricity & Magnetism: Held office hours and graded homework (2018S)
• Graduate Courses
- IC CAD Lab: Led weekly labs on ASIC flow experiments (Analog & Digital) (2018F, 2019F)
- CMOS VLSI Design: Provided office hours and evaluated homework (2022S, 2024S)
- Semiconductor Memory Design: Assisted in guest lectures (SK Hynix) and graded exams (2021S, 2023S, 2025S)