Embedded Files
2023- 24 EVEN SEMESTER (6th Sem ECE)
2023- 24 EVEN SEMESTER (6th Sem ECE)
Start Date: 29/04/2024
Start Date: 29/04/2024
End Date: 31/07/2024
End Date: 31/07/2024
COURSE COORDINATOR:
COURSE COORDINATOR:
DR. SHASHANK M GOWDA
Associate Professor, Dept. of ECE, YIT, Moodbidri.
VLSI DESIGN & TESTING 21EC63 - SYLLABUS
VLSI DESIGN & TESTING 21EC63 - Course Exit Survey(CES)
VLSI LAB 21ECL66 - Course Exit Survey(CES)
COURSE OUTCOME's OF 21EC63 VLSI DESIGN & TESTING
COURSE OUTCOME's OF 21EC63 VLSI DESIGN & TESTING
21EC63.1: Understand the fundamental concepts of MOS transistors, CMOS Logic and analyze the behavior of MOS Transistors under conditions.
21EC63.2: Understand the processes, layout design rules involved in CMOS fabrication and analyze .the factors influencing delay in CMOS circuits.
21EC63.3: Understand the various types of semiconductor memories and their applications.
21EC63.4: Develop test generation technique for combinational logic circuits by understanding different types of faults.
21EC63.5: Design and Develop testable sequential circuits with enhanced controllability and observability.
CO PO and PSO Mapping
PO 1, 2, 3, 4, 5 and PSO 1 and 2
TEXT BOOK 1: “CMOS Digital Integrated Circuits: Analysis and Design” - Sung-Mo Kang & Yusuf Leblebici, Third Edition, Tata McGraw—Hill.
TEXT BOOK 1: “CMOS Digital Integrated Circuits: Analysis and Design” - Sung-Mo Kang & Yusuf Leblebici, Third Edition, Tata McGraw—Hill.
TEXT BOOK 2: “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste and David Money Harris, 4th Edition, Pearson Education.
TEXT BOOK 2: “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste and David Money Harris, 4th Edition, Pearson Education.
NPTEL VIDEO PLAYLIST- Design and Analysis of VLSI Subsystems refer this video playlist to get more in-depth knowledge about the subject.
NPTEL VIDEO PLAYLIST- Design and Analysis of VLSI Subsystems refer this video playlist to get more in-depth knowledge about the subject.
Additional Tool- Memory Matrix
**Advanced Learners- Advanced Assignment- Refer the Link1 and Link2 and create your EDA Playground account.
-> Implement a Priority Encoders using EDA Playground
MODULE 1
MODULE 1
Assignment 1 Questions
Derive a Model relating the current and voltage (I-V) for an nMOS transistor in each of the three regions of operation. - 15 Marks
Explain in detail the DC Characteristics of Static CMOS inverter. - 15 Marks
MODULE 2
MODULE 2
Know More about VLSI Fabrication Process- Video Link
Assignment 2 Questions
Illustrate with neat diagram Equivalent RC Delay Model of an Inverter. 15Marks
Define Logical Effort and find the logical effort of Inverter, 3 Input NAND gate and 3 Input NOR Gate. 15Marks
MODULE 3
MODULE 3
MODULE 4
MODULE 4
MODULE 4 TEXT - PART 2
MODULE 5
MODULE 5
Question Bank
Illustrate how a sequential circuit can be tested as iterative combinational circuits with relevant illustrations.
Define and explain the terms controllability and observability with an example.
Write a note on Random Access Scan(RAS) Methodology.
What is Partial Scan and explain in detail the structure of Partial Scan Design with Two Separate Clocks.
Explain Ad- Hoc Design Rules for Improving Testability with relevant diagrams.
Explain in detail the Scan-Path Technique for Testable Sequential Circuit Design.
Explain the step- by- step procedure for testing a sequential circuit using the extra control input.
VLSI LAB 21ECL66
VLSI LABORATORY 21ECL66 - SYLLABUS
VLSI LABORATORY 21ECL66 RUBRICS FOR EVALUATION
Download the file, Print and Stick in the record before coming to lab exam on 5th and 6th Aug 2023
COURSE OUTCOME's OF 21ECL66 VLSI LABORATORY
COURSE OUTCOME's OF 21ECL66 VLSI LABORATORY
21ECL66.1: Develop skills for observing and verifying the experiment's details and to write clear lab records.
21ECL66.2: Design, simulate, and synthesize digital circuits including a 4-Bit Adder, 4-Bit Booth Multiplier, and 32-Bit ALU, demonstrating proficiency in Verilog coding, functional verification, synthesis techniques, and understanding critical paths.
21ECL66.3: Design and analyze CMOS analog circuits including Inverter, 2-Input CMOS NAND gates, Common Source Amplifiers with PMOS Current Mirror Loads, and Two-Stage Operational Amplifiers, demonstrating proficiency in CMOS circuit design, simulation, and analysis.
21ECL66.4: Gain the sound knowledge about ASIC Digital Design, ASIC Analog Design, fabrication, layout, and analysis of digital and analog circuit.
21ECL66.5: Design, simulate, and perform functional verification of 4- bit carry look ahead adder, design CMOS NOR gate and perform analysis.
PO 1, 2, 4, 5, 12 and PSO 1 and 2
CO PO and PSO Mapping
VERILOG PROGRAMMES IN EDA PLAYGROUND
VERILOG PROGRAMMES IN EDA PLAYGROUND
VERILOG HDL REFERENCE VIDEO PLAYLIST - LINK
GETTING STARTED WITH EDA PLAYGROUND - LINK
LEVELS OF ABSTRACTION IN VERILOG HDL - LINK
TEMPLATE FOR WRITING TEST BENCH_COMBINATIONAL LOGIC BLOCK - LINK
TEMPLATE FOR WRITING TEST BENCH_SEQUENTIAL LOGIC BLOCK - LINK
SIMPLE AND GATE IN DATAFLOW MODELING STYLE - LINK
2 to 4 DECODER USING NAND GATE ONLY_DATAFLOW - LINK
2 to 4 DECODER USING NAND GATE ONLY_GATE LEVEL - LINK
PROGRAM 1- 1 Bit Full Adder
PROGRAM 1- 1 Bit Full Adder
module FULL_ADD_1_BIT(
output sum,
output carry,
input a,
input b,
input cin
);
assign sum=a^b^cin;
assign carry= a&b|a&cin|cin&b;
endmodule
-------------------------------
Test Bench
module FULL_ADD_1_BIT_TEST;
// Inputs
reg a;
reg b;
reg cin;
// Outputs
wire sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
FULL_ADD_1_BIT uut (
.sum(sum),
.carry(carry),
.a(a),
.b(b),
.cin(cin)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a=0;b=0;
#100 a=1;b=0;
#100 a=0;b=1;
#100 a=1;b=1;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 2- 4 Bit Adder- Carry Propagate
PROGRAM 2- 4 Bit Adder- Carry Propagate
module FULL_ADER_4_BIT(
output [3:0]sum_4,
output carry_4,
input [3:0]a_4,
input [3:0]b_4,
input cin_4
);
FULL_ADD_1_BIT FA0 (sum_4[0], C0, a_4[0], b_4[0], cin_4);
FULL_ADD_1_BIT FA1 (sum_4[1], C1, a_4[1], b_4[1], C0);
FULL_ADD_1_BIT FA2 (sum_4[2], C2, a_4[0], b_4[0], C1);
FULL_ADD_1_BIT FA3 (sum_4[3], carry_4, a_4[0], b_4[0], C2);
endmodule
module FULL_ADD_1_BIT(
output sum,
output carry,
input a,
input b,
input cin
);
assign sum=a^b^cin;
assign carry= a&b|a&cin|cin&b;
endmodule
--------------------------------------------------------------------------
Test Bench
module FULL_ADDER_4_BIT_TEST;
// Inputs
reg [3:0] a_4;
reg [3:0] b_4;
reg cin_4;
// Outputs
wire [3:0] sum_4;
wire carry_4;
// Instantiate the Unit Under Test (UUT)
FULL_ADER_4_BIT uut (
.sum_4(sum_4),
.carry_4(carry_4),
.a_4(a_4),
.b_4(b_4),
.cin_4(cin_4)
);
initial begin
// Initialize Inputs
a_4 = 0;
b_4 = 0;
cin_4 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a_4 = 4'b0010; b_4 = 4'b1100; cin_4 = 0;
#100 a_4 = 4'b0011; b_4 = 4'b1100; cin_4 = 0;
#100 a_4 = 4'b0010; b_4 = 4'b1100; cin_4 = 1;
#100 a_4 = 4'b0011; b_4 = 4'b1100; cin_4 = 1;
#100 $finish;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 3- 4 Bit Carry Look Ahead Adder
PROGRAM 3- 4 Bit Carry Look Ahead Adder
module CLA_ADDER_4BIT(a,b,cin,sum,cout);
input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c0,c1,c2,c3,c4;
assign p0=(a[0]^b[0]), p1=(a[1]^b[1]), p2=(a[2]^b[2]), p3=(a[3]^b[3]);
assign g0=(a[0]&b[0]), g1=(a[1]&b[1]), g2=(a[2]&b[2]), g3=(a[3]&b[3]);
// CALCULATING SUM
assign sum[0]=p0^c0, sum[1]=p1^c1, sum[2]=p2^c2, sum[3]=p3^c3;
// CALCULATING CARRY
assign c0=cin;
assign c1=g0|(p0&cin);
assign c2=g1|(p1&g0)|(p1&p0&cin);
assign c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin);
assign c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
assign cout=c4;
endmodule
-----------------------------------------------------------------------------------------
Test Bench
module CLA_ADDER_4BIT_TEST;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
CLA_ADDER_4BIT uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a = 4'b0010; b = 4'b1100; cin = 0;
#100 a = 4'b0011; b = 4'b1100; cin = 0;
#100 a = 4'b0010; b = 4'b1100; cin = 1;
#100 a = 4'b0011; b = 4'b1100; cin = 1;
#100 $finish;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 4- Up/ Down Counter 4 Bit- Asynchronous
PROGRAM 4- Up/ Down Counter 4 Bit- Asynchronous
module up_down_4_bit_counter_async(input clk, reset, up_down, output reg[3:0] count= 4'b0000);
always @(posedge clk or posedge reset)
begin
if(reset)
count <= 4'b0;
else if(up_down)
count <= count + 4'b1;
else
count <= count - 4'd1;
end
endmodule
----------------------------------------------------------------
Test Bench
module up_down_4_bit_counter_async_test;
// Inputs
reg clk;
reg reset;
reg up_down;
// Outputs
wire [3:0] count;
// Instantiate the Unit Under Test (UUT)
up_down_4_bit_counter_async uut (
.clk(clk),
.reset(reset),
.up_down(up_down),
.count(count)
);
initial
begin
clk = 0;
forever #5 clk= ~clk;
end
initial
begin
reset=0;
up_down=1;
#32;
reset = 1;
#40
reset = 0;
#60;
up_down = 0;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 5- Up/ Down Counter 32 Bit- Asynchronous
PROGRAM 5- Up/ Down Counter 32 Bit- Asynchronous
module up_down_counter(input clk, reset,up_down, output[31:0] counter);
reg [31:0] counter_up_down;
always @(posedge clk or posedge reset)
begin
if(reset)
counter_up_down <= 32'h0;
else if(up_down)
counter_up_down <= counter_up_down + 32'd1;
else
counter_up_down <= counter_up_down - 32'd1;
end
assign counter = counter_up_down;
endmodule
---------------------------------------------------------
Test Bench
module COUNTER_32_BIT_TEST;
// Inputs
reg clk;
reg reset;
reg up_down;
// Outputs
wire [31:0] counter;
// Instantiate the Unit Under Test (UUT)
up_down_counter uut (
.clk(clk),
.reset(reset),
.up_down(up_down),
.counter(counter)
);
initial
begin
clk = 0;
forever #5 clk= ~clk;
end
initial
begin
reset=1;
up_down=1;
#20;
reset = 0;
#200;
up_down = 0;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 6- Up/ Down Counter 4 Bit- Synchronous
PROGRAM 6- Up/ Down Counter 4 Bit- Synchronous
module COUNTER_4_BIT_SYNC(input clk, reset, up_down, output reg[3:0] count= 4'b0000);
always @(posedge clk)
begin
if(reset)
count<= 4'b0;
else if(up_down)
count <= count + 4'b1;
else
count <= count - 4'd1;
end
endmodule
----------------------------------------------------------
Test Bench
module COUNTER_4_BIT_SYNC_TEST;
// Inputs
reg clk;
reg reset;
reg up_down;
// Outputs
wire [3:0] count;
// Instantiate the Unit Under Test (UUT)
COUNTER_4_BIT_SYNC uut (
.clk(clk),
.reset(reset),
.up_down(up_down),
.count(count)
);
initial
begin
// Initialize Inputs
clk = 0;
forever #5 clk= ~clk;
end
initial
begin
reset=0;
up_down=1;
#32;
reset = 1;
#40
reset = 0;
#60;
up_down = 0;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 7- Tristate Buffer
PROGRAM 7- Tristate Buffer
module buffer_tristate( input a, en, output reg y);
always @(en,a)
begin
if (en)
y<=a;
else
y<=1'bz;
end
endmodule
-----------------------------------------------------
Test Bench
module buffer_tristate_test;
// Inputs
reg a;
reg en;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
buffer_tristate uut (
.a(a),
.en(en),
.y(y)
);
initial begin
// Initialize Inputs
a = 0;
en = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a = 0;
en = 0;
#10
a = 1;
en = 0;
#10
a = 0;
en = 1;
#10
a = 1;
en = 1;
#10
a = 0;
en = 1;
#10
a = 1;
en = 1;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 8- 32 Bit ALU
PROGRAM 8- 32 Bit ALU
module ALU_32_BIT(a,b,opcode,result);
input[31:0] a,b;
input[2:0]opcode;
output reg[31:0] result;
always @(a,b,opcode)
begin
case(opcode)
3'b000:result=a+b;
3'b001:result=a-b;
3'b010:result=a+1;
3'b011:result=a-1;
3'b100:result=a;
3'b101:result=~a;
3'b110:result=a|b;
3'b111:result=a&b;
default:result=32'b0;
endcase
end
endmodule
-----------------------------------------------------------------
Test Bench
module ALU_32_BIT_TEST;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg [2:0] opcode;
// Outputs
wire [31:0] result;
// Instantiate the Unit Under Test (UUT)
ALU_32_BIT uut (
.a(a),
.b(b),
.opcode(opcode),
.result(result)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
opcode = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a=5; b=6; opcode= 3'b 000;
#100 opcode= 3'b 001;
#100 opcode= 3'b 010;
#100 opcode= 3'b 011;
#100 opcode= 3'b 100;
#100 opcode= 3'b 101;
#100 opcode= 3'b 110;
#100 opcode= 3'b 111;
#100 $finish;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 9_A- D FLIP FLOP
PROGRAM 9_A- D FLIP FLOP
module d_ff (
input clk,
input reset,
input d,
output reg q,
output qb
);
always @(posedge clk)
begin
if (reset)
q = 1'b0;
else
q = d;
end
assign qb = ~q;
endmodule
-----------------------------------------------------------------
Test Bench
module D_FF_TEST;
// Inputs
reg clk;
reg reset;
reg d;
// Outputs
wire q;
wire qb;
// Instantiate the D Flip-Flop (UUT)
d_ff uut (
.clk(clk),
.reset(reset),
.d(d),
.q(q),
.qb(qb)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// Test sequence
initial begin
reset = 0;
d = 0;
#5 reset = 1;
#5 reset = 0;
#5 d = 1;
#10 d = 0;
#25
$finish;
end
endmodule
-----------------------------------------------------------------
OUTPUT WAVEFORM
PROGRAM 9_B- T FLIP FLOP
PROGRAM 9_B- T FLIP FLOP
module t_ff (
input clk,
input reset,
input t,
output reg q,
output reg qb
);
always @(posedge clk)
begin
if (reset)
q = 1'b0;
else if (t)
q = ~q;
else
q = q;
end
assign qb = ~q;
endmodule
-----------------------------------------------------------------
Test Bench
module t_ff_test;
// Inputs
reg clk;
reg reset;
reg t;
// Outputs
wire q;
wire qb;
// Instantiate the T Flip-Flop (UUT)
t_ff uut (
.clk(clk),
.reset(reset),
.t(t),
.q(q),
.qb(qb)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// Test sequence
initial
begin
reset = 0;
t = 0;
#5 reset = 1;
#5 reset = 0;
#5 t = 1;
#25
$finish;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 9_C- SR FLIP FLOP
PROGRAM 9_C- SR FLIP FLOP
module sr_ff (
input s,
input r,
input reset
input clk,
output reg q,
output reg qb
);
always @(posedge clk) begin
if (reset)
q = 0;
else
if (s == 0 && r == 0) q = q;
else if (s == 0 && r == 1) q = 0;
else if (s == 1 && r == 0) q = 1;
else if (s == 1 && r == 1) q = 1'bx;
end
assign qb = ~q;
endmodule
-----------------------------------------------------------
Test Bench
module sr_ff_test;
reg s, r, reset, clk;
wire q, qb;
// Instantiate the SR Flip-Flop
sr_flip_flop uut (
.s(s),
.r(r),
.reset(reset),
.clk(clk),
.q(q),
.qb(qb)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// Test sequence
initial begin
// Initial values
s = 0;
r = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;r=1;
#5 s = 1;r=0;
#5 r = 1;
#30 $finish;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
PROGRAM 9_D- JK FLIP FLOP
PROGRAM 9_D- JK FLIP FLOP
module jk_ff (
input j,
input k,
input reset,
input clk,
output reg q,
output reg qb
);
always @(posedge clk)
begin
if (reset)
q = 0;
else
if (j == 0 && k == 0) q = q;
else if (j == 0 && k == 1) q = 0;
else if (j == 1 && k == 0) q = 1;
else if (j == 1 && k == 1) q = ~q;
end
assign qb = ~q;
endmodule
-----------------------------------------------------------
Test Bench
module jk_ff_test;
reg j, k, clk;
wire q, qb;
// Instantiate the JK Flip-Flop
jk_ff uut (
.j(j),
.k(k),
.reset(reset),
.clk(clk),
.q(q),
.qb(qb)
);
// Clock generation
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
// Test sequence
initial
begin
// Initial values
j = 0;
k = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;k=1;
#5 j = 1;k=0;
#5 k=1;
#50 $finish;
end
endmodule
----------------------------------------------
OUTPUT WAVEFORM
INVERTER SCHEMATIC & LAYOUT
INVERTER SCHEMATIC & LAYOUT
INVERTER_DC_SCHEMATIC
INVERTER_DC_WAVEFORM
INVERTER_TRANS_SCHEMATIC
INVERTER_TRAN_WAVEFORM
INVERTER_LAYOUT
LVS REPORT
2 INPUT NAND SCHEMATIC & LAYOUT
2 INPUT NAND SCHEMATIC & LAYOUT
NAND_SCHEMATIC
NAND_WAVEFORM
NAND_LAYOUT
LVS REPORT
2 INPUT AND SCHEMATIC & LAYOUT
2 INPUT AND SCHEMATIC & LAYOUT
AND_SCHEMATIC
AND_WAVEFORM
AND_LAYOUT
2 INPUT NOR SCHEMATIC & LAYOUT
2 INPUT NOR SCHEMATIC & LAYOUT
NOR_SCHEMATIC
NOR_WAVEFORM
NOR_LAYOUT
2 INPUT OR SCHEMATIC & LAYOUT
2 INPUT OR SCHEMATIC & LAYOUT
OR_SCHEMATIC
OR_WAVEFORM
OR_LAYOUT
LVS REPORT
Common Source Amplifier SCHEMATIC & LAYOUT
Common Source Amplifier SCHEMATIC & LAYOUT
Refer this video for the design calculation write the theory and calculation part of the common source amplifier in the record
Video Link: https://www.youtube.com/watch?v=fEhNSik-HME
In the circuit which is shown in the images below,
--> The W/L Ratio for NMOS is 10/2
--> The W/L Ratio for PMOS is 5/50
--> Overall gain of the amplifier is 10 in Theoretical Calculation
--> In Practical we are achieving the gain as 12 or 13 which is very near to the theoretical calculation.
LT SPICE CODE:
Vdd vdd 0 DC 5
vin vin 0 DC 5
.dc vin 0 1.5 .1
Vdd vdd 0 DC 5
vin vin 0 sin (0.9 0.005 1K 0 0 0 50)
.tran 0 5m
Vdd vdd 0 DC 5
vin vin 0 ac sin (0.9 0.005 1K 0 0 0 50)
.ac dec 100 100 10G
.include D:\ELECTRIC VLSI SOFTWARE\vlsi_vIDEOS-20231027T042647Z-001\vlsi_vIDEOS\ELECTRIC_VLSI\C5_models.txt
.END
Common Source Amplifier_SCHEMATIC
Common Source Amplifier_WAVEFORM_DC to find the bias voltage
Common Source Amplifier_WAVEFORM_TRANSIENT- The graph shows the input magnitude- note the magnitude
Common Source Amplifier_WAVEFORM_TRANSIENT to find the Gain of the amplifier- note the output magnitude and calculate the gain by dividing output magnitude by input magnitude.
Common Source Amplifier_WAVEFORM_AC to find the frequency response= 62.7MHz at 19.61dB
Common Source Amplifier_LAYOUT
LVS REPORT
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Vision of the Department
Vision of the Department
To inspire innovations so as to carve a niche in the field of Electronics & Communication Engineering by inculcating a spirit of creative thinking and train the students in present technologies to meet industrial as well as social needs.
Mission of the Department
Mission of the Department
1. To continuously keep abreast with current trends and technology that support the students to excel in the area of Electronics & Communication Engineering.
2. Provide ethical and value based education by promoting activities addressing the social and industrial needs.
3. Equip students with a steady foundation in Electronics & Communication technology concepts to enable them for continuing education.
Program Educational Objectives (PEO's)
Program Educational Objectives (PEO's)
1 .Graduates will excel in professional career or higher education by acquiring required up to date knowledge in area of Electronics & Communication Engineering.
1 .Graduates will excel in professional career or higher education by acquiring required up to date knowledge in area of Electronics & Communication Engineering.
2. Graduates will be able to analyze real life problems, design appropriate systems to provide solutions that are technically sound, economically feasible and socially acceptable.
3. Graduates will be able to exhibit professionalism, ethical attitude, communication skills and team work and adapt to current trends by engaging in lifelong learning.
Program Specific Outcomes (PSO's)
Program Specific Outcomes (PSO's)
1. Graduates will be able to analyze and design analog & digital circuits using fundamentals of electronics engineering and build systems which will be useful for the society.
2. Implement functional blocks of hardware and software for signal processing and communication applications along with automation systems to process different signals.
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