Research Grants

GRANTS

1. “CyberTraining: Implementation: Small: Promoting AI Readiness for Machine-Assisted Secure Data Analysis (PAIR4MASDA)”, National Science Foundation, PI: A. Fong, co-PIs: S.Bhattacharjee, A. Gupta, K.C. Chen and S. Carr, $499,876.

2. “CyberTraining: Pilot: Modular experiential learning for secure, safe and reliable AI (MELSSRAI)”, National Science Foundation, PI: A. Fong, co-PIs: S. Bhattacharjee, A. Gupta and S.Carr, $298,257, 08/20– 07/22.

3. “VACCS: Visualization and Analysis for C Code Security”, National Science Foundation, PI: S. Carr, co-PIs: J. Mayo, C.-K. Shene, Z. Yang, $300,000 (WMU: $170,000), 01/16 – 12/19.

4. ‘Adaptive Memory Resource Management in a Data Center – A Transfer Learning Approach”, National Science Foundation, PI: L. Brown, co-PIs: Z. Wang and S. Carr, 9/14 – 8/17, $400,000 (WMU: $100,000).

5. “Accessible Access Control”, National Science Foundation, PI: J. Mayo, co-PIs: S. Carr, C.-K. Shene, C. Wang, 9/13 – 8/15, $199,164 (WMU:$40,000).

6. “Accelerated Processor Unit (APU) Software for Convex Optimization”, Advanced Micro Devices, PI: S. Carr, co-PIs: S. Nooshabadi and Z. Wang, $2,000.

7. “Compiler Evaluation for the PowerPC 476 Processor”, LSI Corporation, co-PIs: Steve Carr and Zhenlin Wang, 5/10 – 8/10, $18,215.

8. “Feedback-Directed Resource Management in Virtual Private Machines”, National Science Foundation, co-PIs: Steve Carr and Zhenlin Wang, 9/08 – 12/10, $60,000.

9. “A Performance Model for Partitioned Global Address Space Languages”, National Science Foundation, PI: Steven R. Seidel, co-PIs: Steve Carr and Zhenlin Wang, 9/08 – 8/10, $70,000.

10. “Compiler Development for the Agere Payload Plus network processor”, Agere Systems, PI, 9/04 - 12/05, $85,267.

11. “ITR: Exposing the Compiler to the Hardware: Memory Subsystem Optimizations Through

Compiler/Micro-architecture Cooperation using Set Membership Information and Color Sets”, National Science Foundation, PI: Soner Onder, co-PI: Steve Carr, 9/03 - 8/06, $280,000.

12. “Compilation for the Agere APP5xx and APP7xx Family of Network Processors”, Agere

Systems, PI, 1/03 - 12/03, $62,068.

13. “High-Level Optimization for DSP Architectures” National Science Foundation, PI, 9/02 - 8/05, $249,964.

314. “Concurrent Computing in an Upper-Level Computer Science Curriculum”, National Science Foundation, PI, co-PIs: Jean Mayo and C.-K. Shene, 6/00 - 5/03, $299,865.

15. “Code Generation for ILP Architectures with Partitioned Register Files”, National Science Foundation, PI: Philip H. Sweany, co-PI: Steve Carr, 7/98 - 6/02, $325,434.

16. “Teaching Multithreaded Programming to Computer Science Undergraduates”, National Sci- ence Foundation, PI: C.K. Shene, co-PI: Steve Carr, 3/98 - 5/99, $50,002.

17. “Register-Bank Assignment for Distributed-Register, Instruction-Level Parallel Architectures”, Texas Instruments, PI: Philip H. Sweany, co-PI: Steve Carr, 9/97 - 8/98, $42,830.

18. “Generating Efficient Code for Horizontal Micro-Architectures with Partitioned Register

Files”, Texas Instruments, PI: Philip H. Sweany, co-PI: Steve Carr, 9/95-8/96, $23,715.

19. “Hiding the Latency Between Level-1 and Level-2 Cache on the DEC Alpha 21164”, Digital Equipment Corporation, PI, co-PI: Philip H. Sweany, 7/95-8/97, $137,647.

20. “Improving Memory Performance on the Hewlett-Packard PA-RISC”, Hewlett-Packard Com-

pany, PI, 9/94-8/95, $53,480.

21. “Improving the Cache Performance of Scientific Applications”, National Science Foundation, PI, 7/94-6/97, $90,984.

22. “Cache-Conscious Loop Unrolling”, Hewlett-Packard Company, PI, 7/93, $41,984.