1.     Manikanta K, U Nanda, Interface Trap Charges Impact on Ambipolarity of the Reverse T-Shaped Channel TFET, 2023 International Conference on Next Generation Electronics (NEleX), Vellore, India, 14-16 December 2023.

2.     Manikanta K, U Nanda, Bhaskara Rao K, Design and Performance Assessment of Dielectrically Modulated Reverse T-Shaped TFET Biosensor, 2023 International Conference on Next Generation Electronics (NEleX), Vellore, India, 14-16 December 2023.

3.     Dharani Buddha, P Venkat Sharma, U Nanda, Performance Comparison of Charge Pump Circuits Against Dickson CPs for PLL Application, 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS), Bhubaneswar, September, 2023.

4.     A Biswasa, G Sa, U Nanda, D Sharma, L D Sharma, P Kuswiradyo,  Real-Time American Sign Language Interpretation Using Deep Convolutional Neural Networks, Advances in Distributed Computing and Machine Learning. Lecture Notes in Networks and Systems, vol 660, June 2023, pp. 209–220. (Foreign colaboration)

5.     P Rout, U Nanda, D K Panda, C C Hsu, Design and Comparison of Wideband Cascode Low Noise Amplifier using GAAJLFET and GAA-NC-JLFET for RFIC Applications, 3rd International Conference on Artificial Intelligence and Signal Processing (AISP), Vijayawada, India, Mar 18-20, 2023, pp. 1-5. (Foreign colaboration)

6.     A Yalla, U Nanda, C K Pandey, S Ye, Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic, 3rd International Conference on Artificial Intelligence and Signal Processing (AISP), Vijayawada, India, Mar 18-20, 2023, pp. 1-6. (Foreign colaboration)

7. P Rout, U Nanda, D Kumar, Design and Modeling of a Label-free JLTFET Based Biosensor for Enhanced Sensitivity, IEEE Devices for Integrated Circuit (DevIC), 7-8 April, 2023, Kalyani, India, pp. 77-81.

8. K R N Karthik, C K Pandey, Avatar Singh, U Nanda, Source Extended GaSb/GaAs Heterojunction GAATFET to Improve ION/IOFF ratio, International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 26-27 November, 2022, pp. 469-473. (Foreign colaboration)

9.     Dharani Buddha, U Nanda, and Biswajit Jena, Performance analysis of CSVCO using CMOS and Beyond CMOS Technologies - A Review, International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 26-27 November, 2022, pp. 415-420.

10.  Y Alekhya, U Nanda, “Strategical Survey on Static Random Access Memory: A Bibilometric Study”, 2nd International Conference on Intelligent Technologies (CONIT), Karnataka, India. June 24-26, 2022

11.  P. Raut, U. Nanda, D. K. Panda and H. P. T. Nguyen, "Performance Analysis of Double Gate Junctionless TFET with respect to different high-k materials and oxide thickness," 2nd International Conference on Artificial Intelligence and Signal Processing (AISP), Vijayawada, India, Feb 12-14, 2022, pp. 1-5. (Foreign colaboration)

12.  J. K. Panigrahi, D. P. Acharya and U. Nanda, "Performance Analysis of Dual Threshold CMOS based Current Starved Voltage Controlled Oscillator - A Review," 2nd International Conference on Artificial Intelligence and Signal Processing (AISP), Vijayawada, India, Feb 12-14, 2022, pp. 1-4.

13.  A. Anirudh, U. Nanda and M. Biswal, "Power and Area Efficient Multi-operand Binary Tree Adder," 2nd International Conference on Artificial Intelligence and Signal Processing (AISP), Vijayawada, India, Feb 12-14, 2022, pp. 1-6.

14.  R Singh, K. K. A. Majeed, U Nanda, Transmission Gate Based PFD Free of Glitches for Fast Locking PLL with Reduced Reference Spur. International Conference on Microelectronic Devices, Circuits and Systems, ICMDCS, pp. 404-414, 2021.

15.  U. Nanda, D. Nayak, S. K. Saw, A. Majeed K K and B. Jena, "Analysis of Static Noise Margin of 10T SRAM Using Sleepy Stack Transistor Approach," 2021 Devices for Integrated Circuit (DevIC), pp. 242-246, 2021.

16.  K. Bhol, B. Jena, U. Nanda and S. Tayal, "Work-Function Modulated GAA MOSFET for Improved Electrostatic Controllability in Lower Technology Node," 2021 Devices for Integrated Circuit (DevIC), pp. 270-274, 2021.

17.  U Nanda, A Biswas, KLG Prathyusha, S Gaurav, VSL Samhita, S S Mane, S Chatterjee, J Kumar, Automated Plant Robot, Advances in Distributed Computing and Machine Learning, Vellore, India, pages 107-112, 2020.

18.  Nitin K Mucheli ; U Nanda ; D Nayak ; P K Rout ; S K Swain ; S K Das ; S M Biswal, Smart Power Theft Detection System, Devices for Integrated Circuits (DevIC), pages 302-305 , 2019.

19.  A. Yalla and U. Nanda, Quasi FGMOS Inverter: A Strategy for low power applications, Devices for Integrated Circuits (DevIC), Kalyani, India, pages 211-215, 2019.

20.  S K Das, S K Swain, S M Biswal, D Nayak, U Nanda, B Baral, D Tripathy, Effect of High-K Spacer on the Performance of Gate-Stack Uniformly doped DG-MOSFET, Devices for Integrated Circuits (DevIC), Kalyani, India, pages 365-369, 2019.

21.  S K Swain, S K Das, S M Biswal, S Adak, U Nanda, A A Saha, D Nayak, B Baral, D Nayak, Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET, Devices for Integrated Circuits (DevIC), Kalyani, India, pages 510-514, 2019.

22.  S M Biswal, S K Swain, B Baral, D Nayak, U Nanda, S K Das, D Tripathy, Performance Analysis of Staggered Heterojunction based SRG TFET biosensor for health IoT application, Devices for Integrated Circuits (DevIC), Kalyani, India, pages 493-496, 2019.

23.  D Nayak, U Nanda, P K Rout, S M Biswal, D Tripthy, S K Swain, B Baral, S K Das, A Novel Driver less SRAM with Indirect Read for Low Energy Consumption and Read Noise Elimination, Devices for Integrated Circuits (DevIC), Kalyani, India, pages 314-317, 2019.

24.  U Nanda, D Nayak, S K Pattnaik, S K Swain, S M Biswal, B Biswal, Design and Performance Analysis of Current Starved Voltage Controlled Oscillator, Microelectronics, Electromagnetics and Telecommunications, Springer Nature, Pages 235-246, 2018.

25.  S M Biswal, S K Swain, J R Sahoo, A K. Swain, K Routaray, U Nanda, A Comparative Study of Junctionless Triple-Material Cylindrical Surrounding Gate Tunnel FET, Microelectronics, Electromagnetics and Telecommunications, Springer Nature, pages 793-801, 2018.

26.  S K Swain, S M Biswal, U Nanda, D. S Patro, S K Nayak, B Biswal, Impact of p-GaN Gate Length on Performance of AlGaN/GaN Normally-off HEMT Devices, Microelectronics, Electromagnetics and Telecommunications, Springer Nature, pages 803-809, 2018.

27.  S. K. Pattnaik, U. Nanda, D. Nayak, S. R. Mohapatra, A. B. Nayak and A. Mallick, "Design and implementation of different types of full adders in ALU and leakage minimization," 2017 International Conference on Trends in Electronics and Informatics (ICEI), Tirunelveli, India, pp. 924-927, 2017.

28.  S. N. Panda, S. Padhi, V. Phanindra, U. Nanda, S. K. Pattnaik and D. Nayak, "Design and implementaton of SRAM macro unit," 2017 International Conference on Trends in Electronics and Informatics (ICEI), Tirunelveli, India, pp. 119-123, 2017.

29.  U Nanda, D P Acharya, An Efficient Technique for Low Power Fast Locking PLL Operating in Minimized Dead Zone Condition, IEEE International Conference on Devices for Integrated Circuits, 2017, 23-24 March, 2017, Pages:396-400, Kalyani, India.

30.  U Nanda, S K Pattnaik, Universal Asynchronous Receiver & Transmitter, IEEE International Conference on Advanced Computing and Communication Systems, January, 2016, Pages:1-5, Coimbatore, India.

31.  U Nanda, D P Acharya, S K Patra, Design of a low noise PLL for GSM application, IEEE International conference on  Circuits, Controls and Communications (CCUBE), 27 to 28 Dec 2013,  Pages:1-5, Bangalore, India, .

32.  U Nanda, D P Acharya, S K Patra, P K Rout, Design of Low Power 3.3-4 GHz LC VCO using CMODE, IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology ( ICE-CCN 2013), India during 25th to 26th March, 2013, Pages:717-720, Tamilnadu,.

33.  P K Rout, U Nanda, D P Acharya, G Panda, Design of LC VCO for optimal figure of merit performance using CMODE, IEEE International conference on RAIT-2012, 15th to 17th March, 2012, Pages: 761 – 764, ISM Dhanbad.

34.  U Nanda, K K Mahapatra, Optimization of an application specific Instruction set processor using application Description language, IEEE International Conference on Industrial and Information Systems , ICIIS(2010), Pages:325-328, NIT, Suratkal held on July 28th, 2010.

35.  U Nanda, K K Mahapatra, Design of an Application Specific Instruction Set Processor Using LISA, International Conference on Advanced Computing and Communication, Kerala, May- 2010.

36.  U Nanda, K K Mahapatra, Design of a FIR Filter using Application Description Language, IEEE Sponsored National Conference on Wireless Communication and VLSI Design, Gwalior, March-2010.