My current research focuses on the decoding algorithms and architectures for low-density parity-check (LDPC) codes. This topic is only for my last semester at OSU and it is started from Jan. 2022. 

For my PhD study, I majorly work on the algorithmic and architectural design for the decoding of Generalized Integrated Interleaved (GII) codes. The GII codes are advanced error-correcting codes with excellent performance and can enable hyper-speed data failure recovery in distributed storage systems. However, the decoder design has some bottlenecks, especially the latency in higher-level decoding and the area complexity. In the past years, I have successfully resolved the key latency bottleneck by algorithmic reformulations and also reduced the area complexity substantially. Besides, for short GII-BCH codes targeting practical storage-class memory applications, I have developed efficient schemes to detect/mitigate miscorrections and closed the performance gap between the actual and theoretical decoders. The latency and area issues of such short GII-BCH codes have also been addressed by proposed schemes.

Research projects:

• Performance optimization for data failure recovery in distributed storage systems

• Decoding algorithm/architecture design for data failure recovery in distributed storage systems

Journal

• Xinmiao Zhang and Zhenshan Xie, Sparsity-aware medium-density parity-check decoder for McEliece cryptosystems, IEEE Trans. Circuits Syst. II: Exp. Briefs, in press.

• Zhenshan Xie, Yok Jye Tang, and Xinmiao Zhang, Low-latency nested decoding for short generalized integrated interleaved BCH codes, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 30, no. 10, pp. 1563-1567, Jun. 2022.

• Zhenshan Xie and Xinmiao Zhang, Efficient sub-codeword key equation solver for generalized integrated interleaved BCH decoder, IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 69, no. 1, pp. 85-89, Jan. 2022.

• Zhenshan Xie and Xinmiao Zhang, Miscorrection mitigation for generalized integrated interleaved BCH codes, IEEE Commun. Lett., vol. 25, no. 7, pp. 2118-2122, Jul. 2021. 

• Zhenshan Xie and Xinmiao Zhang, Fast nested key equation solvers for generalized integrated interleaved decoder, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 68, no. 1, pp. 483-495, Jan. 2021.

• Zhenshan Xie and Xinmiao Zhang, Reduced-complexity key equation solvers for generalized integrated interleaved BCH decoders, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 67, no. 12, pp. 5520-5529, Dec. 2020.

• Zhenshan Xie and Xinmiao Zhang, Scaled nested key equation solver for generalized integrated interleaved decoder, IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 67, no. 11, pp. 2457-2461, Nov. 2020.

• Xinmiao Zhang and Zhenshan Xie, Efficient VLSI architectures for coupled-layered regenerating codes, IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 67, no. 10, pp. 1869-1873, Oct. 2020.

• Xinmiao Zhang and Zhenshan Xie, Relaxing the constraints on locally recoverable erasure codes by finite field element variation, IEEE Commun. Lett., vol. 23, no. 10, pp. 1680-1683, Oct. 2019.

• Xinmiao Zhang and Zhenshan Xie, Efficient architectures for generalized integrated interleaved decoder, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 66, no. 10, pp. 4018-4031, Oct. 2019.

Reviewer

• IEEE Journal on Selected Areas in Information Theory

• IEEE Communications Letters

• IEEE Transactions on Circuits and Systems II: Express Briefs

• IEEE Access

• Circuits, Systems, and Signal Processing