Yusang Chun

Education

• Ph.D. EECS, Oregon State University, Corvallis, OR, USA (Sep. 2016 ~ Jun. 2020)

  • Advisor: Prof. Tejasvi Anand

• M.S. EECS, Seoul National University, Seoul, Korea (Sep. 2011 ~ Aug. 2013)

  • Thesis: "Design of All-Digital PLL using Time-to-Digital Converter with 2x Time Amplifier and Vernier Ring"

  • Advisor: Prof. Deog-Kyoon Jeong

• B.S. EECS, KAIST, Daejeon, Korea (Feb. 2017 ~ Aug. 2011)

Work

• Staff Engineer, MediaTek USA Inc., Irvine CA, USA (Jul. 2020 ~ )

• SerDes PHY design intern, Xilinx, San Jose, CA, USA (May 2019 ~ Aug. 2019)

• Senior Engineer, SK Hynix, Icheon, Korea (Apr. 2015 ~ Aug. 2016)

• Senior Engineer, Pixelplus, Suwon, Korea (Sep. 2013 ~ Mar. 2015)

Publications

1. Henry Park, M. Abdullatif, E. Chen, A. Elmallah, Q. Nehal, M.Gandara, T-B. Liu, A. Khashaba, J. Lee, C-Y. Kuan, D. Ramachandran, R-B. Sun, A. Atharav, Yusang Chun, M. Zhang, D-F. Weng, C-H. Tsai, C-H. Chang, C-S. Peng, S-T. Hsu and T. Ali, "A 4.63pJ/b 112Gbps DSP-based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET", in IEEE Solid-State Circuits Conference 2023, TBA.

2. Yusang Chun, Mohamed Megahed, Ashwin Ramachandran and Tejasvi Anand, "A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 57, no. 5, pp. 1527-1541, May 2022.

3. Mohamed Megahed, Yusang Chun, Zhiping Wang and Tejasvi Anand, "A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8," 2021 Symposium on VLSI Circuits, 2021, pp. 1-2.

4. Zhiping Wang, Mohamed Megahed, Yusang Chun and Tejasvi Anand, "A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit," 2021 Symposium on VLSI Circuits, 2021, pp. 1-2.

5. Yusang Chun and Tejasvi Anand, "An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication--Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit," in IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 567-579, March 2020.

6. Yusang Chun, Ashwin Ramachandran and Tejasvi Anand, "A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS," ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), Cracow, Poland, 2019, pp. 269-272.

7. Yusang Chun and Tejasvi Anand, "A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-4. [Outstanding Student Paper Award Nominated].

8. Ashwin Ramachandran, Yusang Chun, Mohamed Megahed and Tejasvi Anand, "An iPWM Line-Coding Based Wireline Transceiver with Clock Domain Encoding for Compensating up to 27dB Loss While Operating at 0.5-to-0.9V and 3-to-16Gb/s in 65nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 55, no. 7, pp. 1946-1959, July 2020.

9. Dong-Wook Kim, Han-Kyu Chi, Yu-Sang Chun, Myung-Heon Chin, Gyungock Kim and Deok-Kyoon Jeong, "12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS," 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, 2013, pp. 1115-1118.