FPGA-晶片

FPGA (Field Programmable Gate Array) 的全名是現場可編程門陣列，簡單的講，FPGA是可再程式化的晶片，經由軟體設定，就可以建置晶片內電子線路的硬體功能。由於是用硬體執行輸入和輸出的開關，每個指令的執行速度大約是1 ns (0.000000001 sec)，並且可以重複製作硬體電路，所以有平行運算的功能，適合用來處理即發性的事件，例如通訊資料，以及聲音和影像的資料。

在早期的時候，IC設計公司用FPGA來設計大型積體電路，先驗證設計的正確性，然後再送到晶圓代工廠，大量製作ASIC的IC。近年來，由於軟硬體的進步 FPGA的售價降低，而程式編輯軟體也比以前便利許多。因此，FPGA可以應用在醫療器材，增加訊號或影像處理的速度，或增強處理的功能。

本課程將以 Altera Max-10 的 DE-10 Lite board 做教學實驗板，教授這顆FPGA晶片的軟硬體，示範控制LED燈、七段顯示器、記憶體讀寫。

FPGA課程的教學影片

https://www.youtube.com/playlist?list=PLYgGtiVoYLPceYKLRhWWpp6SnIoKYGpHy

授課進度表

週次, 上課日期, 講題

2, 2018-2-26, Introduction, Altera Quartus II Tutorial

3, 2018-3-5, Verilog Language and Blinking LED

4, 2018-3-12, ModelSim and Test Bench

5, 2018-3-19, Verilog language

6, 2018-3-26, Design flow / Verilog language (clock, counter, case)

7, 2018-4-2, Quartus: Creating a System With Qsys, Nios II CPU and Eclipse compiler

8, 2018-4-9, Quartus: Internal clock using PLL / VGA

9, 2018-4-16, Quartus: Signal Tap / ADC

10, 2018-4-23, FFT / Binary to Decimal conversion

11, 2018-4-30, Write POF file to CFM device / Adding Componets to the Nois II system / 5-bit counter

12, 2018-5-7, Quartus: timing constraint

13, 2018-5-14, ModelSim: Asynchronized Circuit

14, 2018/5/21, TimeQuest timing analyzer

15, 2018/5/28, National Instrument - myRIO (Xilinx FPGA)

16, 2018/6/4, Project report

17, 2018/6/11, Project report

18, 2018/6/18, 端午節, 放假一天

Max-10 編號 : 10M50DAF484C7G

Board information:

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=Taiwan&CategoryNo=235&No=1059&PartNo=1

FPGA 程式安裝說明

請先到以下網址, 下載6個檔案 (總共有 5G), 安裝在 64-bit 的PC notebook. (需使用自己的 notebook 上課)

https://drive.google.com/drive/folders/0B55nWMORxAf-OTVEX00zV2c3cjQ

1. FPGA 程式安裝說明

2. DE10-Lite_User_Manual

3. max10-17.0.0.595.qdz

4. ModelSimSetup-17.0.0.595-windows

5. QuartusLiteSetup-17.0.0.595-windows

6. QuartusSetup-17.0.2.602-windows

然後按照【 FPGA 程式安裝說明】檔案內敘述的步驟, 安裝程式. 安裝時間約 1~2 小時.

--------------------------------------------------------------------

參考書籍：Verilog硬體描述語言實務 / 作者：鄭光欽、周靜娟、黃孝祖、顏培仁 / 全華圖書股份有限公司

Cornell University:

ECE 5760 info

http://people.ece.cornell.edu/land/courses/ece5760/index.html

ECE 5760 projects

http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/

課程內容

2, 2018-2-26, Introduction, Altera Quartus II Tutorial

(1) Install Model Sim and Quartus

(2) Altera Quartus II Tutorial v11.1

https://www.youtube.com/watch?v=auQ7wpVH-0Q

(3) Installing Altera usb Blaster Driver

https://www.youtube.com/watch?v=glk73wRVQ-c

(4) Creating a Waveform Simulation for Altera FPGAs (Quartus version 13 and newer)

https://www.youtube.com/watch?v=a8JAkKhxlQI

3, 2018-3-5, Verilog Language and Blinking LED

(1) 數位邏輯實驗Lab2 1 Verilog HDL簡介1

https://www.youtube.com/watch?v=uar8OcmrhVM

(2) Load my_led code

(3) copy project and change to 7-segment LED

(4) [ Verilog Tutorial ] 行為模型的敘述: always, if/else, case 與 for loop

http://puremonkey2010.blogspot.tw/2013/11/verilog-tutorial-always-ifelse-case-for.html

(5) Verilog wire and reg confused

https://www.youtube.com/watch?v=WRJcneq91p0&index=56&list=PL4ESKnxAFdaTligaxVBQmF2rLFnCd6X_5

4, 2018-3-12, ModelSim and Test Bench

(1) Write, Compile, and Simulate a Verilog model using ModelSim (use view buttom to modify windows)

https://www.youtube.com/watch?v=9mpRF6bAY1g

(2) Function Testing with ModelSim Part A

https://www.youtube.com/watch?v=LaDnqy2SVsg

(3) Function Testing with ModelSim Part B

https://www.youtube.com/watch?v=G5sQIOK3s40

(4) Quartus => Processing => start test bench. Add test bench to my_led code

(5) A very good explanation on the software "ModelSim"

https://www.youtube.com/watch?v=Z8whdGa7RtY

5, 2018-3-19, Verilog language

File conversion

(1) [Quartus II] Convert VHDL to bdf schematic

https://www.youtube.com/watch?v=Y7hVgBKLJVU

(2) 23 FPGA adding VHDL component and Verilog component to block diagram

https://www.youtube.com/watch?v=R4IKmbYDkqw

(3) 24 FPGA Convert block diagram to vhdl or verilog

https://www.youtube.com/watch?v=IatSVtbBL5g

Blocking and Non-blocking

(4) Verilog Tutorial 04: Blocking NonBlocking

https://www.youtube.com/watch?v=g381XPy_zx0

(5) Verilog tutorial for beginners 18 : Blocking and Non Blocking assignment

https://www.youtube.com/watch?v=FYkoah1MWH0

6, 2018-3-26

Design flow (Chou) / Verilog language (clock, counter, case)

7, 2018-4-2, Quartus: Creating a System With Qsys, Nios II CPU and Eclipse compiler (S)

Nios II documentation available with your installation at:

<installation_directory>/nios2eds/documents/index.htm.

Lesson 2 | Starting A Project With Altera Quartus II And Creating A System With Qsys

https://www.youtube.com/watch?v=2VL7mHfvoyY

Lesson 3 | Compiling A Project In Quartus II

https://www.youtube.com/watch?v=uPuui9ZhZk8

Lesson 5 | Setting Up And Running A Project In The Nios II Development Tools For Eclipse

https://www.youtube.com/watch?v=c--JenWcXdA

Lesson 6 | Using The Debug Tools In The Nios II Build Tools For Eclipse

https://www.youtube.com/watch?v=Qe2Aoep17H4

------------------------------

Add the following in the *.qsf file:

# For MAX-10

#============================================================

# CLOCK

#============================================================

set_location_assignment PIN_P11 -to CLOCK_50

#============================================================

# LED

#============================================================

set_location_assignment PIN_A8 -to LEDG[0]

set_location_assignment PIN_A9 -to LEDG[1]

set_location_assignment PIN_A10 -to LEDG[2]

set_location_assignment PIN_B10 -to LEDG[3]

set_location_assignment PIN_D13 -to LEDG[4]

set_location_assignment PIN_C13 -to LEDG[5]

set_location_assignment PIN_E14 -to LEDG[6]

set_location_assignment PIN_D14 -to LEDG[7]

set_location_assignment PIN_A11 -to LEDG[8]

set_location_assignment PIN_B11 -to LEDG[9]

#============================================================

# KEY

#============================================================

set_location_assignment PIN_B8 -to KEY[0]

------------------------------

References:

Quartus II + Qsys + Eclipse Hello World (中文)

https://www.youtube.com/watch?v=vrnsSrbiX_Q

Hello World on your FPGA

https://www.youtube.com/watch?v=gBknFw511s0

33 FPGA NIOS II QSYS 03 blinking led (counting led)

https://www.youtube.com/watch?v=VesGiZaCut8

36 FPGA NIOS II QSYS 06 buttons control leds

https://www.youtube.com/watch?v=5-jVCgVx3aI

Altera FPGA tutorial - Controlling LEDs with switches using NIOSII Processor (DE2 Board)

https://www.youtube.com/watch?v=w82xFo1RNmo

Ch_Embedded_Electronic

https://www.youtube.com/channel/UCtVcgyxAbg81d2-9P28_wEw

8, 2018-4-9-a, Quartus: Internal clock using PLL

(1) 1 Hz, DE1 Onboard Clock using Frequency Division in Quartus

https://www.youtube.com/watch?v=sbUAJByFb30

(2) Frequency Division on Altera DE1 board using Quartus II

https://www.youtube.com/watch?v=8R03xz62kQk

(3) what is Phase locked loop? What is the need of it, and how it works? PLL tutorial PLL basics #16

https://www.youtube.com/watch?v=CM8n3wzNOvc

(4) Adding a PLL

https://www.youtube.com/watch?v=V09MmwyKR6U

(5) FPGA create clock with Megawizard in Quartus

https://www.youtube.com/watch?v=5bg_3uelNM0

8, 2018-4-9-b, VGA

(6) Lesson 104 - VGA Controller

https://www.youtube.com/watch?v=wzhDRIX2Ors

(7) FPGA Tutorial 4. VGA in VHDL on Altera DE1 Board

https://www.youtube.com/watch?v=WK5FT5RD1sU&t=276s

9, 2018-4-16-a, Quartus: Signal Tap

-----------------------------------------

if(tmp1 == 32'd3000000)

setup : tmp1(19)

data : tmp2, led_cout

sample depth : 512

-------------------------------------------

Introduction to Using Signal Tap (Very good)

https://www.youtube.com/watch?v=mFwuHhlp-8g

SignalTap demo (no sound)

https://www.youtube.com/watch?v=aQ5JKz-sGfA

9, 2018-4-16-b, ADC

MAX 10 FPGA Analog Block (that is, ADC)

https://www.youtube.com/watch?v=sGR8NH23eDk

How to Create ADC Design in MAX 10 Device Using Qsys Tool

https://www.youtube.com/watch?v=0oO1RFa-4Xk

How to export MAX 10 ADC conversion data to the core for post-processing

https://www.youtube.com/watch?v=u7y5ZR1E8SU

10, 2018-4-23, FFT / Binary to Decimal conversion

(1) How to implement the FFT to iFFT operation with Natural input and output orders using Cosine data

https://www.youtube.com/watch?v=KODAHoJGk4E

--------------------

pwd, ls,

cd C:/../../cv_fft_iff_natural_dreverse_cosine_170/fft0/simulation/mentor

source msim_setup.tcl

do wave.do

run -all (till about 9,000 ns)

--------------------

b2v_inst, b2v_inst6

a, a_tb, count0, fft0, fft1, rom0

---------------------

use quartus, open project, check files, open files

use Qsys, check *.qip

---------------------

Altera FFT IP core

https://www.altera.com/documentation/hco1419012539637.html

https://www.altera.com/documentation/hco1419012539637.html#hco1419012438961

(2) Binary to decimal conversion

11, 2018-4-30, write POF file to CFM device / Adding Componets to the Nois II system (S) / 5-bit counter

(1) Write POF File into the CFM Device (hint: delete .sof, and use .pof in programmer)

See page 69 ~ 72 of the Manual

(2) Adding components to the Nios system

Lesson 7 | Adding System Clock Timer To Qsys and Quartus II

https://www.youtube.com/watch?v=VD3fhdKMueU

Lesson 8 | Adding Paralell I/O (PIO) Red LED's To Qsys and Quartus II

https://www.youtube.com/watch?v=sUlL6kgYPlE

Lesson 9 | Adding Paralell I/O (PIO) Slider Switches To Qsys and Quartus II

https://www.youtube.com/watch?v=Jnrh9IgDlf8

Lesson 10 | Adding Paralell I/O (PIO) Keys (Pushbuttons) With Interrupts To Qsys and Quartus II

https://www.youtube.com/watch?v=j_JFzSRqdew

Lesson 11 | Adding SRAM For DE2-115 To Qsys and Quartus II

https://www.youtube.com/watch?v=gb-vSjPUNyE

Lesson 12 | Adding SDRAM To Qsys and Quartus II

https://www.youtube.com/watch?v=FjuZ3IGNur0&t=133s

Lesson 13 | Adding Paralell I/O (PIO) For Seven Segment Display To Qsys and Quartus II

https://www.youtube.com/watch?v=isObSaq3Eg0

(3) First projects with FPGAs: 5-bit counter

https://www.youtube.com/watch?v=ThXBW27d_ps

14, 2018/5/21, TimeQuest timing analyzer

Experiment:

(1) Getting Started with the TimeQuest Timing Analyzer

https://www.youtube.com/watch?v=bFmTHLZ3DGs

(2) hand-on experiment

-------------------------- my_led.v

create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}]

set_input_delay 3 -clock [get_clocks {clk}] [get_ports select]

set_input_delay 3 -clock [get_clocks {clk}] [get_ports reset]

set_output_delay 10 -clock [get_clocks {clk}] [get_ports cout[*]]

--------------------------

Theory:

(3) Timing Analyzer: Introduction to Timing Analysis (9:17 ~ 13:30)

https://www.youtube.com/watch?v=B73G4BuTpLo

(4) Timing Analyzer: Timing Analyzer GUI (1;09 ~ 12:00)

https://www.youtube.com/watch?v=IGAwgI3Fs-k

(5) Timing Analyzer: Intel® Quartus® Prime Integration & Reporting (skip)

https://www.youtube.com/watch?v=_7mMYhuQIbY

(6) Timing Analyzer: Required SDC Constraints (skip)

https://www.youtube.com/watch?v=hfaiPxl9Z9A

Reference:

TimeQuest and the Synopsis Design Constraint (sdc) File / ece5760 Cornell

https://people.ece.cornell.edu/land/courses/ece5760/Quartus/TimeQuest_sdc_file.html

Adding SDC constraints to a DE1-SOC project

https://www.youtube.com/watch?v=b4STwjT_g1g

#1 DE1-SoC Introduction

https://www.youtube.com/watch?v=sKhvMhTiuM4&list=PLKcjQ_UFkrd7UcOVMm39A6VdMbWWq-e_c

15, 2018/5/28, National Instrument - myRIO (Xilinx FPGA)

NI myRIO 學習資源中心

http://taiwan.ni.com/myrio-resource

參考資料

Altera DE10-Nano 在 AI 的應用

(1) An OpenCL-Based pipe CNN

http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=PR022

(2) 深度学习的眼科疾病诊断系统

http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=PR061&All=1

INTEL 2018 FPGA competition:

http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Code=AP&All=1

FPGA emulates Hammond organ

https://www.youtube.com/watch?v=OOmVIg0raWo

Keyboard partner

http://shop.keyboardpartner.de/epages/13705466.sf/en_GB/?ObjectPath=/Shops/13705466/Categories/HX3-Magazin/Soundbeispiele

FPGA Design and Implementation of Electric Guitar Audio Effects Xilinx XOHW17 XIL-84082 - WINNER

https://www.youtube.com/watch?v=ANxHyCAYGp0

Vladilit/fpga-multi-effect

https://github.com/Vladilit/fpga-multi-effect

推薦影片: FPGA, by Ch_Embedded_Electronic

https://www.youtube.com/playlist?list=PL4ESKnxAFdaTligaxVBQmF2rLFnCd6X_5

推薦影片: FPGA.SeanWRall.com

http://fpga.seanwrall.com/lessons/

官方網站

Google Sites

Report abuse

FPGA-晶片

本課程將以 Altera Max-10 的 DE-10 Lite board 做教學實驗板，教授這顆FPGA晶片的軟硬體，示範控制LED燈、七段顯示器、記憶體讀寫。

FPGA課程的教學影片

授課進度表

週次, 上課日期, 講題

2, 2018-2-26, Introduction, Altera Quartus II Tutorial

3, 2018-3-5, Verilog Language and Blinking LED

4, 2018-3-12, ModelSim and Test Bench

5, 2018-3-19, Verilog language

6, 2018-3-26, Design flow / Verilog language (clock, counter, case)

7, 2018-4-2, Quartus: Creating a System With Qsys, Nios II CPU and Eclipse compiler

8, 2018-4-9, Quartus: Internal clock using PLL / VGA

9, 2018-4-16, Quartus: Signal Tap / ADC

10, 2018-4-23, FFT / Binary to Decimal conversion

11, 2018-4-30, Write POF file to CFM device / Adding Componets to the Nois II system / 5-bit counter

12, 2018-5-7, Quartus: timing constraint

13, 2018-5-14, ModelSim: Asynchronized Circuit

14, 2018/5/21, TimeQuest timing analyzer

15, 2018/5/28, National Instrument - myRIO (Xilinx FPGA)

16, 2018/6/4, Project report

17, 2018/6/11, Project report

18, 2018/6/18, 端午節, 放假一天

Max-10 編號 : 10M50DAF484C7G

Board information:

FPGA 程式安裝說明

請先到以下網址, 下載6個檔案 (總共有 5G), 安裝在 64-bit 的PC notebook. (需使用自己的 notebook 上課)

1. FPGA 程式安裝說明

2. DE10-Lite_User_Manual

3. max10-17.0.0.595.qdz

4. ModelSimSetup-17.0.0.595-windows

5. QuartusLiteSetup-17.0.0.595-windows

6. QuartusSetup-17.0.2.602-windows

然後按照 【 FPGA 程式安裝說明】 檔案內敘述的步驟, 安裝程式. 安裝時間約 1~2 小時.

--------------------------------------------------------------------

參考書籍：Verilog硬體描述語言實務 / 作者：鄭光欽、周靜娟、黃孝祖、顏培仁 / 全華圖書股份有限公司

Cornell University:

ECE 5760 info

ECE 5760 projects

課程內容

2, 2018-2-26, Introduction, Altera Quartus II Tutorial

3, 2018-3-5, Verilog Language and Blinking LED

4, 2018-3-12, ModelSim and Test Bench

5, 2018-3-19, Verilog language

6, 2018-3-26

Design flow (Chou) / Verilog language (clock, counter, case)

7, 2018-4-2, Quartus: Creating a System With Qsys, Nios II CPU and Eclipse compiler (S)

8, 2018-4-9-a, Quartus: Internal clock using PLL

8, 2018-4-9-b, VGA

9, 2018-4-16-a, Quartus: Signal Tap

9, 2018-4-16-b, ADC

10, 2018-4-23, FFT / Binary to Decimal conversion

(1) How to implement the FFT to iFFT operation with Natural input and output orders using Cosine data

(2) Binary to decimal conversion

11, 2018-4-30, write POF file to CFM device / Adding Componets to the Nois II system (S) / 5-bit counter

(1) Write POF File into the CFM Device (hint: delete *.sof, and use *.pof in programmer)

See page 69 ~ 72 of the Manual

(2) Adding components to the Nios system

(3) First projects with FPGAs: 5-bit counter

14, 2018/5/21, TimeQuest timing analyzer

15, 2018/5/28, National Instrument - myRIO (Xilinx FPGA)

參考資料

Altera DE10-Nano 在 AI 的應用

(1) An OpenCL-Based pipe CNN

(2) 深度学习的眼科疾病诊断系统

INTEL 2018 FPGA competition:

FPGA emulates Hammond organ

Keyboard partner

FPGA Design and Implementation of Electric Guitar Audio Effects Xilinx XOHW17 XIL-84082 - WINNER

Vladilit/fpga-multi-effect

推薦影片: FPGA, by Ch_Embedded_Electronic

推薦影片: FPGA.SeanWRall.com

官方網站

然後按照【 FPGA 程式安裝說明】檔案內敘述的步驟, 安裝程式. 安裝時間約 1~2 小時.

(1) Write POF File into the CFM Device (hint: delete .sof, and use .pof in programmer)