Research
Research
"The greatest enemy of knowledge is not ignorance, it is the illusion of knowledge." - Stephen Hawking
1. Performance Analysis of Emerging Forksheet NCFET Devices (Accepted in IEEE TED)
Designing a novel forksheet FET with multiple channels stacked vertically in Silvaco TCAD.
Adding an extra ferroelectric layer of optimized thickness (critical thickness) to introduce negative capacitance (NC).
Simulating the NC FET by solving the 1D L-K equation to obtain the I-V curve of the NC FET.
Measuring different device parameters like threshold voltage, transconductance, On/Off current ratio, subthreshold swing, DIBL, delay, power consumption, etc.
2. Designed nano-textured c-Si solar cells coated with metallic nanoparticles and quantum dots using Lumerical Device Suit (Published in Nanoscale Advances)
DOI: 10.1039/D3NA00436H
Exploring various nanotextured top surface in a C-Si based solar cell. Among all of the nanostructures, parabola shaped nanostructures came out to be the most effective.
Simulating the solar cell in Lumerical Device Suit using FDTD simulations and electrical simulations.
Applying sphere shape Au (gold) particles to introduce the LSPR effect in order to enhance the efficiency of the device.
3. Machine Learning Based Device Modeling and Performance Optimization for Emerging Nanoscale Devices. (Manuscript under preparation)
Designing emerging nanoscale devices like CFET, Forksheet FET, and FinFET in Silvaco TCAD, generating Current vs. Voltage and Capacitance vs. Voltage data.
Collecting data by varying FET geometries and observing device behavior.
Creating machine learning (ML) and deep learning (DL) pipelines to predict device behavior, which can simplify physics-based simulations and accelerate the process.
4. Performance Analysis of MoS2/WSe2 Complementary Field-Effect Transistors for achieving excellent scalability, superior transport properties, and improved short-channel effects (Ongoing Project)
Modeling a 2D FET using Sentaurus TCAD.
Designing monolayer MoS2 and WSe2 FET and calibrating the device behavior with that of fabricated devices in literature.
Simulating the CFET with n-FET vertically stacked over the p-FET and observe different parameters of the final devices.