先進半導體元件實驗室 國立清華大學 工程與系統科學系
Advanced Nanoelectronic X-FET Devices Labortory
National Tsing Hua University, Department of Engineering and System Science
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👍👍👍吳永俊教授團隊榮獲 2025 IEEE Paul Rappaport Award
On behalf of the IEEE Electron Devices Society (EDS), congratulations on being selected as the recipients of the 2025 IEEE EDS Paul Rappaport Award for your paper entitled "Multibit N- and P-type Fe-GAAFETs Using HfO₂/ZrO₂ Superlattice Dielectric and SiGe/Si Superlattice Channel with Record Low Voltage, Large Memory Window, High Speed and Reliability for High Density 1T NVM Applications."
IEEE EDS 官方資料指出，Paul Rappaport Award 自 1984 年設立，現定Paul Rappaport Award 不是由單一研討會自行選出的 Best Paper，而是 IEEE Electron Devices Society 的年度獎項，針對 T-ED 論文進行認可。IEEE EDS 的歷史資料也明確稱其為每年頒發的最佳論文獎。
Semiconductor Processes and Integration
Semiconductor Processes and Integration
Author: Professor Yung-Chun Wu (吳永俊 教授)
Publisher: Cengage; 1st ed. 2026 edition, Softcover: 496 pages
ISBN 978-6267533420
https://www.cengageasia.com/title/default/detail?isbn=9786267533420
半導體製程與整合
半導體製程與整合
!!!半導體製程書籍銷售第一名!!!
Author: 吳永俊(Yung-Chun Wu),
孫崇哲(Chong-Jhe Sun), 顏孝丞(Siao-Cheng Yan)
Publisher: 2023年8月, 滄海圖書資訊
ISBN 978-626-9729-166
榮獲國科會 "2023未來科技獎"
榮獲國科會 "2023未來科技獎"
指導之計畫「三維原子級電子斷層掃描技術在前瞻半導體元件的應用」，對於半導體原子級薄膜可進一步進行分析，提高台灣於半導體產業的競爭力。
EDL Cover page
EDL Cover page
Multilevel Cell Ferroelectric HfZrO FinFET With High Speed and Large Memory Window Using AlON Interfacial Layer. Y. C. Wu* et al., IEEE ELECTRON DEVICE LETTERS, VOL. 44, NO. 1, January 2023.
High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET. Y. C. Wu* et al., Nanomaterials, 13(8), pp. 1310, April 2023.
3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET. Y. C. Wu* et al., IEEE Journal of the Electron Devices Society, vol. 11, pp. 480-484, Aug. 2023.
SiGe/Si Superlattice Ferroelectric HfZrO2 ΩFET and CMOS Inverter with SSmin,n = 62.4 mV/dec, ION/IOFF > 1.0 × 107, and Voltage Gain = 111.4 V/V. Y. C. Wu* et al., IEEE ELECTRON DEVICE LETTERS, VOL. 44, NO. 1, January 2024.
Low-Temperature Microwave Annealing Stabilized Morphotropic Phase Boundary in HfO2/ZrO2 Superlattice Heterostructures. Y. C. Wu* et al., Applied Physics Letters, 126, 232105, June 2025.
Using High Dielectric Constant HfO2/ZrO2 Superlattice Dielectrics to Enhance Ge Stacked Nanosheets Gate-All-Around Transistor Performance. Y. C. Wu* et al., IEEE ELECTRON DEVICE LETTERS, VOL. 46, NO. 7, JULY 2025.
Review of Recent HZO-Based Ferroelectric Transistors for Non-Volatile Memory Applications. Y. -C. Wu and C. -Y. Wei, IEEE Electron Devices Reviews, vol. 2, pp. 361-375, 2025, doi: 10.1109/EDR.2025.3646143.
EDR 是世界頂級的評論期刊，涵蓋電子裝置的各個方面，對研發有著無與倫比的洞察力。此論文為吳永俊教授實驗室近十年於鐵電電晶體與記憶體具體研究成果的回顧文獻。
👍與台積電合作申請2件重要專利與相關營業機密，對台積電3奈米以下世代製程有重要的幫助。
👍三年內發表國際期刊論文14篇，國際研討會論文12篇。
👍中華民國專利發表(2020後)
1.專利編號(證書號): I740465 公告日: 2021/09/21 申請號: TW109113313
公告號: TWI740465B
發明人: 吳永俊 WU, YUNG CHUN; 侯福居HOU; FU-JU; 蔡孟儒TSAI; MENG-JU
專利名稱: 具超薄結晶性氧化鉿鋯之閘極介電層的鐵電電晶體裝置 FERROELECTRIC FET DEVICE WITH ULTRA THIN GATE DIELECTRIC LAYER OF CRYSTALLINITY HFZRO
👍美國專利發表 !!!均與台積電共同獲證!!!
👍美國專利發表 !!!均與台積電共同獲證!!!
1. 公告號: US20240332386A1 公告日:2024/10/03 申請號:US18194379
Inventors: Wu; Yung-Chun (Hsinchu city, TW), Yi-Ju YAO (New Taipei City, TW)
Semiconductor device and manufacturing method thereof
2. 公告號: US20250301784A1 公告日:2025/09/25 申請號:US18611610
Inventors: Yung-Chun WU (Hsinchu City, TW), Fu-Ju HOU (Chiayi County, TW), Yi-Wen LIN (Pingtung County, TW), Shan-Wen LIN (Pingtung County, TW)
Semiconductor device and method for forming the same
3. 公告號: US20260006885A1 公告日:2026/01/01 申請號:US18935794
Inventors: Yung-Chun WU (Hsinchu City, TW), Fu-Ju HOU (Hsinchu City, TW), Yi-Ju YAO (New Taipei City, TW)
Dielectric element and application of the same
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