High-speed/bandwidth interfaces (TCAS-I25, Access25, CICC25, ISSCC25_a, ISSCC25_b)
Low-power/noise clocking (JSSC25, ESSERC24, ESSCIRC23, TCAS-II23, JSSC22)
Privacy-preserving computing (PPAI25, ICCAD24, arXiv22, HPCA21, ISCA18)
ML for systems/circuits (DATE25, arXiv23, TCAS-II23)
Systems/circuits for ML (AICAS22, ISCAS22)
For a complete list of publications, see Google Scholar.
2025
A 0.65-pJ/bit 3.6-TB/s/mm I/O interface with XTalk minimizing affine signaling for next-generation HBM with high interconnect density; Hyunjun Park, Jiwon Shin, Hanseok Kim, Jihee Kim, Haengbeom Shin, Taehoon Kim, Hyeri Roh, Jung-Hun Park, Woo-Seok Choi; TCAS-I
Implementing FFE-MLSD with improved BER and reduced complexity for long-reach PAM4 wireline receivers; Hanseok Kim, Sihyun Lee, Piljun Jeong, Jaeha Kim, Woo-Seok Choi; IEEE Access
A 4x32Gb/s 1.8pJ/bit collaborative baud-rate CDR with background eye-climbing algorithm and low-power global clock distribution; Jihee Kim, Jia Park, Jiwon Shin, Hanseok Kim, Kahyun Kim, Haengbeom Shin, Ha-Jung Park, Woo-Seok Choi; JSSC - Samsung Humantech Paper Award
A 3ns idle-exit latency 0.28-28Gb/s/pin single-ended NRZ die-to-die interface with energy-efficient receiver and background noise compensation; Hyun-Seok Choi, Sunki Cho, Sanghee Lee, Hyeri Roh, Jeong-Eun Song, Honggyoo Ahn, Jihee Kim, Minchang Kim, Hankyu Chi, Deog-Kyoon Jeong, Woo-Seok Choi; CICC
ML-based fast and accurate performance modeling and prediction for high-speed memory interfaces across different technologies; Taehoon Kim, Minjeong Kim, Hankyu Chi, Byungjun Kang, Eunji Song, Woo-Seok Choi; DATE
Flash: A hybrid private inference protocol for deep CNNs with high accuracy and low latency on CPU; Hyeri Roh, Jinsu Yeo, Yeongil Ko, Gu-Yeon Wei, David Brooks, Woo-Seok Choi; PPAI (Extended version in arXiv)
A 42Gb/s single-ended hybrid-DFE PAM-3 receiver for GDDR7 memory interfaces; Boram Kim, Hankyu Chi, Hyeongjun Ko, Sangyeon Byeon, Sungkwon Lee, Changhyun Pyo, Seulgi Kim, Byungjun Kang, Eunji Song, Kwangjin Na, Jinyoup Cha, Hyesoo Kim, Shinyoung Park, Woo-Seok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim; ISSCC
A 0.275pJ/b 42Gb/s/pin clock-referenced PAM3 transceiver tolerant to supply noise, reference offset and crosstalk for chiplets and short-reach memory interfaces; Kahyun Kim, Jung-Hun Park, Ha-Jung Park, Jia Park, Jihee Kim, Woo-Seok Choi; ISSCC
2024
Hyena: Optimizing homomorphically encrypted convolution for private CNN inference; Hyeri Roh, Woo-Seok Choi; ICCAD - CEDA/ICCAD Grant Award
An 8GHz 9bit phase-rotating ILCM with DTC range reduction for high-speed serial links; Jia Park, Jihee Kim, Sanghee Lee, Kahyun Kim, Ha-Jung Park, Woo-Seok Choi; ESSERC
2023
NeuralEQ: Neural-network-based equalizer for high-speed wireline communication; Hanseok Kim, Jae Hyung Ju, Hyun Seok Choi, Hyeri Roh, Woo-Seok Choi; arXiv
A near-threshold ring-oscillator-based ILCM with edge-selective error detector achieving -64dBc reference-spur and -239dB FOM; Jiwon Shin, Joonghyun Song, Jihee Kim, Woo-Seok Choi; ESSCIRC
A context-aware readout system for sparse touch sensing array using ultra-low-power always-on event detection; Hyeri Roh, Woo-Seok Choi; TCAS-II
Phase noise analysis for stochastically injected oscillators; Jiwon Shin, Woo-Seok Choi; TCAS-II
Fast performance evaluation methodology for high-speed memory interfaces; Taehoon Kim, Yoona Lee, Woo-Seok Choi; DATE
2022
Impala: Low-latency communication-efficient private deep learning inference; Woo-Seok Choi, Brandon Reagen, Gu-Yeon Wei, David Brooks; arXiv
A residue-current-locked hybrid low-dropout regulator supporting ultralow dropout of sub-50mV with fast settling time below 10ns; Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong, Jun-Eun Park; JSSC
0.41-pJ/b/dB asymmetric simultaneous bidirectional transceivers with PAM-4 forward and PAM-2 back channels for 5-m automotive camera link; Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong; VLSI
Energy-efficient high-accuracy spiking neural network inference using time-domain neurons; Joonghyun Song, Jiwon Shin, Hanseok Kim, Woo-Seok Choi; AICAS - Best Paper Award
A low-jitter 8-GHz RO-based ADPLL with PVT-robust replica-based analog closed loop for supply noise compensation; Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong; JSSC
Improving spiking neural network accuracy using time-based neurons; Hanseok Kim, Woo-Seok Choi; ISCAS - CAS Travel Grant Award
2021
Cheetah: Optimizing and accelerating homomorphic encryption for private inference; Brandon Reagen*, Woo-Seok Choi*, Yeongil Ko, Vincent T. Lee, Hsien-Hsin S. Lee, Gu-Yeon Wei, David Brooks; HPCA - IEEE Micro Top Picks Honorable Mention
2020
A 12-Gb/s 10-ns turn-on time rapid on/off baud-rate DFE receiver in 65nm CMOS; Dongwook Kim, Mostafa Ahmed, Woo-Seok Choi, Ahmed Elkholy, Pavan Kumar Hanumolu; JSSC
2019
A 0.016mm2 0.26-uW/MHz 60-240-MHz digital PLL with delay-modulating clock buffer in 65nm CMOS; Junheng Zhu, Woo-Seok Choi, Pavan Kumar Hanumolu; JSSC
A 15-Gb/s sub-baud-rate digital CDR; Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu; JSSC
2018
Guaranteeing local differential privacy on ultra-low-power systems; Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte, Pavan Kumar Hanumolu, Rakesh Kumar; ISCA
A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR; Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu; CICC - Outstanding Student Paper Nominee
A 0.45-0.7V 1-6Gb/s 0.29-0.58pJ/b source-synchronous transceiver using near-threshold operation; Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu; JSSC
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based Buck converter with seamless transition between PWM/PFM modes; Seong Joong Kim, Woo-Seok Choi, Robert Pilawa-Podgurski, Pavan Kumar Hanumolu; JSSC
2017
A 5GHz digital fractional-N PLL using a 1-bit Delta-Sigma frequency-to-digital converter in 65nm CMOS; Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu; JSSC
A 2.8mW/Gb/s 14Gb/s serial link transceiver; Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrummay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu; JSSC
A 3-to-10Gb/s 5.75pJ/bit transceiver with flexible clocking in 65nm CMOS; Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu; ISSCC
2016
A 4-to-10.5-Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS; Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu; JSSC
A 16Mb/s-8Gb/s, 14.1-5.9pJ/bit source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS; Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu; ISSCC
2015
A 2.8mW/Gb/s 14Gb/s transceiver in 65nm CMOS; Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrummay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu; VLSI
A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method; Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu; JSSC
A 3.7mW low-noise wide-bandwidth 4.5GHz digital fractional-N PLL using time amplifier based TDC; Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu; JSSC
A burst-mode digital receiver with programmable input jitter filtering for energy proportional links; Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu; JSSC
A 0.45-to-0.7V 1-to-6Gb/s 0.29-to-0.58pJ/bit source-synchronous transceiver using automatic phase calibration in 65nm CMOS; Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu; ISSCC
2014
A 4.25-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement; Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu; VLSI
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz in-band noise using time amplifier based TDC; Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu; VLSI
A 4.4-5.4GHz digital fractional-N PLL using Delta-Sigma frequency-to-digital converter; Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu; VLSI
A reference-less clock and data recovery circuit using phase-rotating phase-locked loop; Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu; JSSC
A 4-to-10.5-Gb/s 2.2-mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS; Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu; ISSCC
2013
A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR; Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu; VLSI
A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering; Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Pavan Kumar Hanumolu; VLSI
2011
250Mbps - 5Gbps wide-range CDR with digital Vernier phase shifting and dual-mode control in 0.13um CMOS; Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong; JSSC