this text was generated by AI, and while I can assure that most of the time I am alucinating, I cannot do the same regarding the quality of it. It is based on the change log up to beta 30 on public information available on the WinUAE 6.0.0 beta series thread.
The core theme is a significant move towards cycle-accurate and low-level emulation of the Amiga chipset (Agnus, Denise, Alice), departing from previous hack-based or shortcut methods.
This rewrite aims for higher compatibility and fidelity, particularly in handling complex and cycle-sensitive demos, games, and operating system behaviors.
While initial beta versions introduced performance overheads, later updates, particularly Beta 8 onwards and the introduction of multi-threading in Beta 13, have significantly improved performance, often exceeding previous WinUAE versions, especially in non-cycle-exact modes and RTG configurations.
The process is ongoing, with a final release estimated for summer 2025 or later.
The core of these updates revolves around a complete rewrite of the Amiga chipset emulation, moving from high-level approximations to detailed, low-level simulation.
Key themes include:
Cycle-Accurate Emulation: The primary goal is to emulate the chipset at a much finer granularity, down to the individual clock cycle (CCK) and even logic gate level for some components. This allows for accurate reproduction of timing-sensitive behaviors that were previously impossible or required specific hacks.
Hardware-Inspired Architecture: The new code is based on real hardware schematics (specifically Alice schematics are mentioned) and separates components like Agnus and Denise with data transfer via an emulated RGA bus, mimicking the physical hardware.
Removal of Hacks and Shortcuts: Older code built on approximations and specific fixes for problematic software has been replaced with a cleaner, more accurate model. This simplifies the codebase and improves handling of previously unknown or edge-case behaviors.
Focus on Low-Level Details: Emulation now includes fine-grained details like DMA slot selection shift registers, DMA conflicts, horizontal and vertical blanking/sync signals (including programmed and hardwired mixing), VPOSW/VHPOSW on-the-fly modifications, interlace detection based on real display behavior, and detailed blitter micro-operation timing (though still being refined).
Improved Compatibility: The increased accuracy aims to improve compatibility with demos, games, and software that rely on precise chipset timing and undocumented features. "All usual badly coded demos (blitter modifications mid blit etc) should all work."
Performance Optimization (Post-Rewrite): The initial rewrite introduced performance regressions, particularly in fast CPU modes. Subsequent beta versions have focused heavily on regaining and improving performance through line-based optimizations, skipping drawing of unchanged lines (in non-cycle-exact modes), and crucially, multi-threaded emulation of the Denise/Lisa rasterization.
Accurate Keyboard Emulation: A significant addition is the optional hardware-level emulation of various Amiga keyboard microcontrollers (6570-036, 68HC05C, D8039HLC). This provides accurate behavior, including handshake timings, key ghosting, and the specific caps lock flashing trick used by some demos.
3. Most Important Ideas and Facts:
Complete Chipset Rewrite (v6): This is the fundamental change. The emulation is no longer a collection of hacks but a simulation of the chipset's internal workings.
AVX2 Host CPU Requirement (Initially): The initial beta versions required a host CPU with AVX2 support (around 2015+). This was a temporary measure to facilitate development and testing, and the requirement has since been lowered back to SSE2 in later betas. "Host CPU requirement bumped to AVX2 (~2015+ CPUs). This is just arbitrary decision to cut off "too old" CPUs for now until things get better."..."CPU requirement is back to SSE2."
Performance Improvements (Beta 8+): A major hurdle after the rewrite was performance. Beta 8 marked a turning point with "Major optimization included, WB native modes... are now much faster". Beta 10 included "most planned non-ce mode optimizations," aiming for parity or better performance than older versions.
Multi-threaded Denise/Lisa Emulation (Beta 13): This is highlighted as a significant performance boost. By moving the rasterization process to a separate thread, WinUAE can leverage multi-core processors more effectively. "Major performance improvement! Finally faster than older versions!"
Cycle-Exact Mode Overhead: While performance has improved overall, the most accurate "Memory cycle-exact" mode still incurs a higher overhead compared to non-cycle-exact modes due to the continuous cycle-by-cycle simulation. "Memory cycle-exact enabled: always cycle-by-cycle chipset mode, high chipset emulation overhead."
Accurate Sync and Blanking Emulation: This low-level detail is crucial for correct display synchronization and compatibility with demos that manipulate these aspects. "Horizontal and vertical blanking and sync start/end, csync, csync equalization pulses, etc are now fully cycle-accurately emulated..."
VPOSW/VHPOSW Flexibility: The new emulation removes limitations on VPOSW/VHPOSW modifications, allowing for more complex and "Ross special screen modes."
Accurate Blitter Emulation: Efforts are being made to achieve 100% accuracy in the blitter channel sequencer and later, micro-operation timings. "Blitter channel sequencer should be now 100% accurate..."
Hardware Keyboard Emulation: This provides a highly accurate simulation of keyboard behavior, including specific MCU quirks and the caps lock flashing effect. "Optional hardware level keyboard emulation! (*). Odyssey / Alcatraz CAPS LOCK flashing is finally supported."
Removal of Software Filters: As part of the optimization efforts and the move towards direct rendering, software filters have been removed. "All software filters removed."
Handling of Chipset Quirks: The updates address numerous specific, and sometimes obscure, chipset behaviors and glitches, such as NTSC STRLONG effects, BPL1DAT timing differences, and mid-screen BPLCON0 changes.
Ongoing Development: The beta nature and the estimated release date (summer 2025 or later) indicate that this is a complex and lengthy development process with ongoing refinements and bug fixes.
4. Specific Changes and Fixes of Note:
Performance:WB native mode performance restored and improved (b8, b10).
CE mode performance improved, now faster than 5.3.1 (b13).
RTG mode performance restored to pre-v6 levels (b6).
Line-based optimizations for static or mostly static screens (b7, b8, b10, b11).
Multi-threaded Denise/Lisa emulation (b13).
Chipset Accuracy:Removed custom chipset emulation hacks, replaced with new code based on Alice schematics (common).
Full RGA pipeline emulation (common).
Separated Agnus/Denise with emulated RGA bus (common).
Accurate DMA slot emulation and conflict handling (common).
Cycle-accurate sync and blanking emulation (Display).
VPOSW/VHPOSW modifications fully supported (Display).
Accurate interlace detection (Display).
Full AGA hires/shres granularity (Display).
ECS Agnus/AGA UHRES bitplane/sprite DMA slots emulated (Display).
Various timing fixes for COPJMP, BPL1DAT, BPLCON0 changes, NTSC STRLONG (Display).
Blitter:Improved channel sequencer accuracy (Blitter).
Accurate block mode D channel scheduler logic (Blitter).
Correct handling of mid-blit BLTxMOD/BLTCON1 toggling (Blitter).
Accurate BLTZERO timing (Blitter).
Keyboard:Optional hardware-level emulation of different keyboard MCUs (Keyboard).
Accurate key matrix reading and serial code transfer (Keyboard).
Support for caps lock flashing trick (Keyboard).
Misc:Improved on-the-fly chipset type switching (Misc).
Easy and cheap even to odd bitplane collision emulation (Misc).
Extended DMA debugger capabilities (Misc).
Added RIPPLE IDE controller emulation (Misc).
Improved CD32 CD read behavior (b7, b8).
Added Matrox PCI graphics card emulation (b7).
Added A1000 512k WOM expansion emulation (b15).
Improved handling of real harddrives/memory cards with MBR/RDB partitions (b12, b15, b16, b30).
Fixes for various display glitches and artifacts across many betas.
Integer scale and automatic scaling improvements (b20, b22, b23, b24, b26).
Serial port emulation updates (b15, b17, b20).
5. Known Issues and TODOs:
Some blitter special cases in old statefiles might not work anymore (Testing Examples).
CPU odd cycle COPJMP + blitter active conflict is still not fully correct (Display).
Internal interleaved shifter side-effects in OCS/ECS Denise are not emulated fully (Display).
Blitter "micro-operation" timings are not yet 100% accurate (Blitter).
Performance improvements in CE modes for blitter or copper might be possible (b13).
Detecting and optimizing lines with "simple" copper activity (TODO).
Emulating normal DMA mode sprites in line-based mode (TODO).
NTSC right edge glitches in fast modes (b13, b21, b27, b28, b29).
Multi-threaded RTG blitter operations could be more optimal (eab comment).
Need to decide how to handle the right edge horizontal scrolling glitch (b27, b28, b29).
Lagless vsync needs v6 chipset emulation update (b28).
Paula serial port emulation is still under rewrite (b15, b17, b20).
Display port monitors (like A2024) need more updates (b23).
6. Conclusion:
The v6 chipset emulation rewrite in WinUAE represents a significant undertaking to achieve a higher level of accuracy and fidelity in Amiga emulation. The initial performance challenges are being addressed through ongoing optimizations and the adoption of multi-threading. While still in beta and with some known issues and areas for further refinement, these updates have already resulted in improved compatibility with complex Amiga software and often better performance than previous versions, particularly in common usage scenarios outside of cycle-exact modes. The development continues with a focus on completing the low-level emulation and further optimizing performance across all modes.
The core philosophy behind WinUAE v6 was a radical departure from previous development. Instead of relying on cumulative "hacks and shortcuts," the focus was on building a completely new foundation for custom chipset emulation based on the original Alice schematics.
The explicit goal was to make the code "much simpler and easier to understand" and, most importantly, to have it work "more closely like real HW," even emulating "Some signals... in almost logic gate level." This commitment to ground-up accuracy was a deliberate move to create a more maintainable and authentic emulation.
A significant change was the complete separation of Agnus and Denise emulation. Data transfer between these chips is now handled "via emulated external RGA bus," accurately reflecting the hardware design. This includes using "Strobe registers used for chip syncronization like on real HW. No more shortcuts," and fully emulating the "Internal RGA pipeline."
This detailed RGA handling and chip separation are considered crucial for correctly timing the data flow between these vital components.
The initial consequence of the deeply accurate, ground-up rewrite was a performance decrease, particularly in "fast CPU modes." This was an anticipated trade-off for the push for accuracy. Early betas (like Beta 2 and 3) focused on fixing immediate issues arising from this new complexity, such as AGA sprite rendering and HAM mode problems, and implementing "Copper/Blitter conflict fixes." To compensate for the new data flow demands on faster CPUs, a "longer RGA pipeline" was introduced in Beta 3 to prevent overflows.
Reclaiming performance was a multi-stage process.
For RTG modes, Beta 6 restored speed by skipping "Almost all chipset emulation code" when the native Amiga screen wasn't visible.
For native Amiga modes, "line-based emulation" was introduced in Beta 7, initially by not redrawing unchanged lines (like vblank or static backgrounds).
Beta 8 significantly extended this by skipping redraws if a scanline "has bitplanes but it has not changed since last frame and line has no copper activity and no sprites," which "restores performance compared to previous WinUAE versions when mostly static native display is visible."
Further optimizations in later betas included drawing "directly from chip ram (bypassing DMA emulation)" for minor changes and implementing specific "fast modes" for display types like "HAM6, HAM8, DPF and EHB" using "optimized generated code (genlinetoscr)," bringing the host "CPU requirement is back to SSE2" for non-cycle-exact modes.
The most significant performance improvement came with the implementation of multithreading in Beta 13. This involved placing "Denise side processing... in separate thread," which includes graphics rendering tasks like bitplane shifting, sprite processing, and planar to chunky conversion. This was made possible by the earlier "cleanly separates Agnus and Denise logic and Denise is almost fully 'fire and forget.'"
This architectural change allowed Denise's work to be offloaded and processed in parallel, leading to "Major performance improvement! Finally faster than older versions!" and allowing the removal of the "previously always used temporary graphics buffering... only done if needed."
The v6 cycle allowed for deep dives into specific Amiga hardware quirks and features. A major addition is the "Optional hardware level keyboard emulation," which emulates the keyboard's microcontroller to support complex behaviors like "Odyssey / Alcatraz CAPS LOCK flashing."
Display accuracy saw significant improvements, with "Horizontal and vertical blanking and sync start/end, csync... now fully cycle-accurately emulated" and full support for "VPOSW/VHPOSW on the fly modifications," even enabling the opening of the Amiga's "hardwired 'borders' with cycle-accurate CPU timing."
NTSC-specific behaviors like the "LOL (long line) state" and "STRLONG behavior" across different chip versions were also tackled. The Blitter was refined with the "channel sequencer should be now 100% accurate" and the "block mode D channel scheduler logic now matches real behavior." New hardware emulation includes the "RIPPLE IDE controller emulation," an "A1000 512k WOM expansion emulation," and PCI cards like the "Matrox Millennium" series.
While "Uncompromising Accuracy" is the primary driver, the development acknowledges that in optimized "fast CPU modes," perfect replication of every obscure hardware glitch might not always be feasible or desirable if it significantly impacts performance. For instance, regarding the "right edge horizontal scrolling glitch" in Beta 29, a pragmatic choice was made: "Fast CPU modes 'fixes' the glitch," while accurate modes still show the original behavior.
This illustrates that in fast modes, some very specific, niche behaviors may be sacrificed for broader compatibility and usability, as these modes "inherently can't have all the information that the full cycle-accurate path does."
The overarching vision for WinUAE, as demonstrated by the v6 cycle, revolves around several key pillars.
The first is "Uncompromising Accuracy," aiming to emulate the Amiga hardware as closely as possible, based on schematics and even near logic-gate level detail. This is coupled with "Accuracy with Performance," ensuring that this deep accuracy is delivered in a usable state, with the multithreading and optimization efforts being central to this.
The goal is also "Rock-Solid Stability and Compatibility," enabling WinUAE to reliably run the widest range of Amiga software and hardware configurations.
Finally, the focus on a cleaner, "much simpler and easier to understand" codebase contributes to the "Longevity and Maintainability" of the project, making future development and potential contributions easier.