Edge AI Accelerator
Reconfigurable Systems
Low Power Circuits and Systems
FPGA/VLSI/Verilog HDL
Smart Wearable Devices and Systems
Design for Mission-critical and Harsh Environments
The lab is developing an edge AI accelerator system with a user-friendly framework involving instruction sets, and control software design. Currently, the team is also cooperating with an analog team to develop mix-signal edge AI devices. On the other hand, the team is also seeking a possible method to shorten the RTL design to market time by utilizing machine learning. Overall, the interesting topics are listed below:
Edge AI accelerator system development (Utilizing FPGA or cell-based ASIC)
Efficient software framework for edge AI accelerator (Utilizing C or Python and Verilog)
Digital circuit design to handle analog input signals for AI computation
Machine learning for RTL design
The lab is looking for master students with machine learning and/or hardware experimental backgrounds, and the undergraduate trainees are also welcome.
If you are interested in Edge AI hardware design, you are encouraged to join the lab. Feel free to contact Dr Weison Lin by email.
Refer to the page for master program enrollment and scholarship.