Composable Hardware Research Lab (CHRL)
Vikram Jain
Incoming Assistant Professor (Fall 2026),
Electrical and Computer Engineering, Purdue University
Postdoc & Lecturer,
University of California, Berkeley
PhD, MICAS, KU Leuven
Email: vikramj@purdue.edu
🚨 I am seeking highly motivated prospective PhD students to join my team for Fall 2026 at the ECE department, Purdue University. Please email me your CV at vikramj@purdue.edu if you are interested.
About me
Long biography Vikram CV
I am currently a Postdoctoral researcher in SpeciaLIzed Computing Ecosystem (SLICE) Lab and Berkeley Wireless Research Center (BWRC) of the University of California, Berkeley. I am also a lecturer in the EECS department at UC Berkeley. I taught EE194-290: IC Design Project class, Spring 2025, which aims to teach students how to tapeout chips in a semester. I also co-instructed EE290-2 Hardware for Machine Learning course at UC Berkeley with Prof. Sophia Shao. My current research focuses on AI accelerators, hardware-software co-design, heterogeneous integration, and chiplet (2.5D and 3D) architectures for emerging high-performance computing and AI applications. I obtained my Ph.D. degree in energy-efficient heterogeneous systems for embedded machine learning (ML) from the MICAS Laboratories at KU Leuven. I was also a Visiting Researcher during my Ph.D. at the IIS Laboratory, ETH Zurich, Zürich, Switzerland, where I worked on the design of high-performance networks-on-chip for DNN platforms.
I have published several papers and posters in top conferences and journals such as ISSCC, JSSC, Sym. on VLSI Technology and Circuits (VLSI), DAC, DATE, ISLPED, ISCAS, TCAS-I, TVLSI, and TComp. I also serve as a reviewer for the IEEE Journal of Solid-State Circuits, IEEE Transaction on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Circuits and Systems I (TCAS-I), and IEEE Internet-of-Things Journal (IoTJ).
I have received the Solid-State Circuits Society (SSCS) Predoctoral Achievement Award for 2022-2023, the SSCS Student Travel Grant in 2022, and the Lars Pareto Travel Grant in 2019. I also received a prestigious research fellowship from the Swedish Institute (SI) for 2016–2017 and 2017–2018 during my master’s program.
Before my Ph.D., I received my M.Sc. degree in embedded electronics systems design (EESD) from the Chalmers University of Technology, Gothenburg, Sweden, in 2018, and my B.Tech degree (silver medal) in Electrical and Electronics Engineering from Sathyabama Institute of Science and Technology, India.
My Research Interests:
AI/ML accelerators; RISC-V architecture; Heterogenous integration; Chiplets (2.5D and 3D); Heterogeneous multi-core systems; Network-on-chips; Design space exploration; Low-power digital design; Hardware design automation; AI for chip design
Recent News
📰 We have three VLSI papers accepted for presentation at the VLSI Symposium on Circuits and Technology 2025, in Kyoto, Japan. Congratulations everyone!