Vikram Jain
Incoming Assistant Professor (Fall 2026),
Composable Silicon Lab,
Elmore School of Electrical and Computer Engineering,
Purdue University
Postdoc & Lecturer, University of California, Berkeley
PhD, MICAS, KU Leuven
Email: vikramj@purdue.edu
About Me:
Long biography Vikram CV
Vikram Jain is an incoming Assistant Professor in the Electrical and Computer Engineering department at Purdue University (Fall 2026). Currently, he is a Principal Engineer at TSMC, San Jose, working on efficient AI acceleration architectures and compute-in-memory design.
Previously, Vikram was a Postdoctoral Researcher and Lecturer at the University of California, Berkeley, within the SLICE Lab and Berkeley Wireless Research Center (BWRC). During his time at Berkeley, he taught the IC Design Project class (guiding students through chip tapeouts) and co-instructed the Hardware for Machine Learning course. He obtained his Ph.D. from KU Leuven (MICAS Laboratories) and was a Visiting Researcher at ETH Zurich.
His research focuses on AI accelerators, hardware-software co-design, and chiplet (2.5D/3D) architectures for high-performance computing. His work has been published in top-tier venues including ISSCC, JSSC, VLSI, HPCA, and DAC. He is a recipient of the SSCS Predoctoral Achievement Award and the Swedish Institute Research Fellowship.
Recent News:
📰 Sirius, our work on Multimodal Embodied AI acceleration using Chiplets, has been accepted for presentation at the 2026 VLSI Symposium on Circuits and Technology, in Honolulu, Hawaii, US. Congratulations everyone!
📰 Cygnus has been accepted for publication in the Journal of Solid-State Circuits.
📰 I have joined the ISLPED 2026 TPC for the Logic and Architectures track.
📰 I have joined the TPC for IEEE MICRO, 2026.
📰 I will be acting as TPC for DAC, a subcommittee of In-memory and near-memory computing architectures, 2026.
📰 I have joined the technical program committee for HPCA, 2026.
📰 I have joined TSMC, San Jose, as a Principal Engineer.
📰 We have three VLSI papers accepted for presentation at the VLSI Symposium on Circuits and Technology 2025, in Kyoto, Japan. Congratulations everyone!