🚨 I am seeking highly motivated prospective PhD students to join my team for Fall 2026 at the ECE department, Purdue University. Please email me your CV at vikramj@purdue.edu if you are interested.
🚨 I am seeking highly motivated prospective PhD students to join my team for Fall 2026 at the ECE department, Purdue University. Please email me your CV at vikramj@purdue.edu if you are interested.
Vikram Jain
Incoming Assistant Professor (Fall 2026),Â
Elmore School of Electrical and Computer Engineering,Â
Purdue University
Postdoc & Lecturer, University of California, Berkeley
PhD, MICAS, KU Leuven
Email: vikramj@purdue.edu
   vikramj@berkeley.edu
   vikramjainiit@gmail.com
Long biography Vikram CVÂ
Vikram Jain is an incoming Assistant Professor in the Electrical and Computer Engineering department at Purdue University (Fall 2026). Currently, he is a Principal Engineer at TSMC, San Jose, working on efficient AI acceleration architectures and compute-in-memory design.
Previously, Vikram was a Postdoctoral Researcher and Lecturer at the University of California, Berkeley, within the SLICE Lab and Berkeley Wireless Research Center (BWRC). During his time at Berkeley, he taught the IC Design Project class (guiding students through chip tapeouts) and co-instructed the Hardware for Machine Learning course. He obtained his Ph.D. from KU Leuven (MICAS Laboratories) and was a Visiting Researcher at ETH Zurich.
His research focuses on AI accelerators, hardware-software co-design, and chiplet (2.5D/3D) architectures for high-performance computing. His work has been published in top-tier venues including ISSCC, JSSC, VLSI, and DAC. He is a recipient of the SSCS Predoctoral Achievement Award and the Swedish Institute Research Fellowship.
AI/ML Accelerators
RISC-V Architecture
Heterogeneous Multi-core Systems
Low-power Digital Design
Chiplets (2.5D and 3D)
Heterogeneous Integration
Network-on-Chips (NoC)
Hardware Design Automation
AI for Chip Design
Design Space Exploration
📰 Will be joining the TPC for DAC, 2025.
📰 Joined the technical program committee for HPCA, 2025.
📰 I joined TSMC, San Jose, as a Principal Engineer.
📰 We have three VLSI papers accepted for presentation at the VLSI Symposium on Circuits and Technology 2025, in Kyoto, Japan. Congratulations everyone!