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About Me
About Me
I'm an M.S./Ph.D. student in Electrical and Computer Engineering at The University of Texas at Austin (UT Austin). I am advised by Professors Gustavo de Veciana and Kaushik Chowdhury. Within UT Austin's ECE department, I'm in the Decision, Information, and Communications Engineering (DICE) track and the Wireless Networking and Communications Group (WNCG).
I graduated with my B.S. in Electrical Engineering at University of California, Los Angeles (UCLA) in Spring 2025. There, I worked in the Cognitive Reconfigurable Embedded Systems (CORES) Lab, under Professor Danijela Cabric. I focused on network-level optimization of Internet of Things (IoT) systems.
Having started at UT Austin in Fall 2025, I'm looking forward to explore resource allocation algorithms for wireless networks.
Education
Education
University of Texas at Austin (UT Austin); Austin, TX.
M.S./Ph.D., Electrical and Computer Engineering, matriculating August 2025.
University of California, Los Angeles (UCLA); Los Angeles, CA.
B.S., Electrical Engineering, June 2025.
GPA: 3.97. UCLA ECE Outstanding Student Award, ECE Fast Track Honors student, Eta Kappa Nu & Tau Beta Pi honors society member.
Work Experience
Work Experience
Astranis Space Technologies, San Francisco, CA | Communications/DSP Engineering Intern, Payload Performance Team (June 2025 – Present)
• Developed hardware data collection tests and corresponding equalization/calibration algorithms to be run on software-defined radio to adjust for phase offsets due to imperfections of multi-port amplifiers in the transmitter chain of geostationary satellites.
Sandia National Laboratories, Livermore, CA | Electrical Engineering R&D Year-Round Intern, Telemetry Department
FIR Filter Design on FPGA (September 2024 – March 2025)
• Investigated embedded implementations of digital filters.
Communication Protocol Digital Design and Verification (June 2024 – September 2024)
• Designed and implemented a generalized SPI communication protocol in VHDL using Vivado, with high-capacity burst read/write functionality from FIFO buffers.
• Conducted design verification of an FPGA program interfacing with multiple ICs using SystemVerilog in Riviera-PRO.
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