EDUCATIONAL  QUALIFICATIONS

• Doctor of Philosophy (Ph.D) – VLSI Device Modeling & Nanotechnology | (2020)

Thiagarajar College of Engineering, Madurai (Anna University, Chennai) 

• Masters of Engineering (M.E) – VLSI DESIGN | (2015) 

P.S.N.A College of Engineering & Technology, Dindigul (Anna University, Chennai) 

• Bachelors of Engineering (B.E) – Electronics & Communication | (2013) 

SACS MAVMM Engineering College, Madurai (Anna University, Chennai) 

TEACHING EXPERIENNCE

• Associate Professor - Department of ECE, CMR Institute of Technology, Bengaluru, Karnataka, India 

(10-06-2022 to Till Date)

• Assistant Professor - School of ECE, REVA University, Bengaluru, Karnataka, India 

(02-08-2021 to 06-06-2022)

• Assistant Professor - Department of ECE, M.Kumarasamy College of Engineering, Karur, Tamil Nadu, India 

(27-07-2020 to 30-07-2021)

• Teaching Assistant  - Department of ECE, Thiagarajar College of Engineering, Madurai, under TEQIP scheme 

(07-06-2016 to 20-12-2019)

AREA OF INTEREST

•  Semiconductor Devices

•  Electronic Circuits

•  CMOS VLSI Systems

• VLSI Device Modeling

• Analog Integrated Circuit Design

• Low Power VLSI Design

•  Nano Scale Devices

•  System On Chip Design

TECHNICAL SKILL SET

Languages: VHDL, Verilog, MATLAB, Basics of C

Designing Software: TCAD, Model SIM, Xilinx ISE, Cadence

PROFESSIONAL MEMBERSHIP DETAILS

• Indian Society for Technical Education (ISTE) - LM131385

•  International Association of Engineers (IAENG)- 272267

• Institute of Scholars (InSc) - InSc20202020

• IEEE Member - 97313074

• The Institution of Electronics & Telecommunication Engineers (IETE)-M-502054

PATENT PUBLISHED & GRANTED

 (i) Title : Novel Germanium Source Single Halo Doped Double Gate TFET for Biosensor Application 

(Indian Patent) Date of Filing of Application : 29/03/2021 Publication Date : 09/04/2021

 (ii) Title: An Novel Method- Intelligent Safe Home System for the Elderly People 

Date of Filing of Application : 21/08/2021 Granted: 19/01/2022 (Australian Patent)

BOOK PUBLICATION

Silicon and Germanium based Halo doped Tunnel Field Effect Transistors

Lap Lambert Academic Publishing (2020), ISBN : 978-620-3-02896-6

JOURNAL PUBLICATIONS

• G.Lakshmi Priya, M. Venkatesh, Lucky Agarwal, T. S. Arun Samuel Modeling and Performance analysis of Nanocavity Embedded Dopingless T‑shaped Tunnel FET with high‑K gate dielectric for biosensing applications, Applied Physics A: Materials Science and Processing 128 (11), 1-11 Springer (SCIE-Indexed), (ISSN: 0947-8396, Impact Factor: 2.983)

• Venkatesh M Priya Lakshmi G, Namita R, Abhishek S, Modeling and Simulation of Double Gate Dielectric Stack Silicon Substrate Memristor Circuits for Low Power Applications Silicon (2022), Springer (SCIE-Indexed), (ISSN: 1876- 9918, Impact Factor: 2.670)

• A. Andrew Roobert, P. Sherly Arunodhayamary, D. Gracia Nirmala Rani, M. Venkatesh, L. Jerart Julus Design and  analysis of 28 GHz CMOS low power LNA with 6.4 dB gain variability for 5G applications, Transactions on Emerging Telecommunications Technologies, Wiley (2022) (SCIE-Indexed), (ISSN: 2161- 3915 ,Impact Factor: 2.638)

• Samuel, T.S.A., Venkatesh, M., Pandian, M.K. et al. Investigation of ON Current and Subthreshold Swing of an InSb/Si Heterojunction Stacked Oxide Double-Gate TFET with Graphene Nanoribbon, Journal of Electronic Materials (2021), https://doi.org/10.1007/s11664-021-09244-5 Springer (SCIE-Indexed), (ISSN: 0361- 5235 ,Impact Factor: 1.938)

• Kumar, T.V., Venkatesh, M., Muthupandian, B. et al. Charge Density Based Small Signal Modeling for InSb/AlInSb Asymmetric Double Gate Silicon Substrate HEMT for High Frequency Applications. https://doi.org/10.1007/s12633-021- 01383-y Silicon (2021), Springer (SCIE-Indexed), (ISSN: 1876-9918, Impact Factor: 2.670)

• Preethi, S., Venkatesh, M., Karthigai Pandian, M. et al. Analytical Modeling and Simulation of Gate-All-Around Junctionless Mosfet for Biosensing Applications. https://doi.org/10.1007/s12633-021-01301-2, Silicon 2021 -Springer (SCIEIndexed), (ISSN: 1876-9918, Impact Factor: 2.670)

• Priya, G.L., Venkatesh, M., Balamurugan, N.B. et al. Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System. Silicon 13, 1691–1702 (2021), Silicon-Springer (SCIE-Indexed), https://doi.org/10.1007/s12633-021-01075-7 (ISSN: 1876-9918, Impact Factor: 2.670)

• M.Venkatesh, G.Lakshmi Priya and N. B Balamurugan (2020),” Investigation of Ambipolar Conduction and RF Stability Performance in Novel Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate TFET”, SiliconSpringer (SCIE-Indexed), https://doi.org/10.1007/s12633-020-00856-w (ISSN: 1876-9918, Impact Factor: 2.670)

• M.Venkatesh and N. B Balamurugan (2020),” Influence of Threshold Voltage Performance analysis on Dual Halo Gate Stacked Triple Material Dual Gate TFET for Ultra Low Power Applications”, Silicon-Springer (SCIE-Indexed), http://link.springer.com/article/10.1007/s12633-020-00422-4 (ISSN: 1876-9918, Impact Factor: 2.670)

• M.Venkatesh, M.Suguna and N. B Balamurugan (2020),” Influence of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET for improved Analog/RF Performance”, Silicon-Springer (SCIE-Indexed), http://link.springer.com/article/10.1007/s12633-020-00385-6 (ISSN: 1876-9918, Impact Factor: 2.670)

• M.Venkatesh and N. B Balamurugan (2019),”New subthreshold performance analysis of germanium based dual halo gate stacked triple material surrounding gate tunnel field effect transistor”, Superlattices and Microstructures – Elsevier(130),485-498,(SCIE-Indexed),https://doi.org/10.1016/j.spmi.2019.05.016 (ISSN: 0749-6036, Impact Factor: 2.658).

• M.Venkatesh, M.Suguna and N. B Balamurugan (2019),” Subthreshold performance analysis of germanium source dual halo dual dielectric triple material surrounding gate tunnel field effect transistor for ultra low power applications”, Journal of Electronic Materials - Springer,https://doi.org/10.1007/s11664-019-07492-0, (SCIE-Indexed) (ISSN: 0361- 5235 ,Impact Factor: 1.938)

• M.Venkatesh, and K.Vinoth Kumar (2020),” Leakage Power Consumption in Domino Circuits For Wide-Fan inputs using high threshold stacked transistors”,International Journal of Engineering Applied Sciences and Technology (ISSN: 2455-2143)

• Venkatesh.M and Karthikeyan.P (2015), “A Novel Technique for Power optimization in Dual Threshold Footerless Domino Logic Circuit”, International Journal of Advanced Research Trends in Engineering and Technology (IJARTET), Volume.2, Special Issue. I, March,(ISSN: 2394-3785)

• Karthikeyan.P, Saravanan.R, Venkatesh.M, Vinothkumar.K (2015), “Analytical Modeling of dual Material surrounding Gate TFET to Reduce Short-Channel Effects for Low Power Applications”, International Journal of Applied Engineering Research (IJAER-Scopus),Volume.10,No.55 (ISSN: 0973-4562,Impact Factor: 0.13)

• Venkatesh.M and Karthikeyan.P (2014), “Review of Two Dimensional Analytical Model of Dual Material Gate Tunnel Field Effect Transistor”, International Journal of Computer Science and Mobile Application (IJCSMA), Volume.2, Issue.11, Pg.143-149(ISSN:2321-8363)

COURSES

BASIC ELECTRONICS