Workshop Description
Vector architectures have been present almost since the beginning of the history of supercomputing. These architectures are able to represent an operation over several data elements with a single instruction, exploiting data-level parallelism (DLP). Data-level parallelism coupled with thread-level parallelism (TLP) are keystones to achieve Exascale computing under a reasonable power budget. DLP and TLP are present in most modern supercomputers, regardless of being based on accelerators (e.g., GPGPUs) and/or CPUs (IBM Vector Media eXtension –VMX–, NEC SX architecture, Intel Advanced Vector eXtension –AVX– and ARM Scalable Vector Extension –SVE–).
Since most general purpose architectures are embracing vector based designs, designers, programming models and languages, tools and libraries must adapt to take full advantage of the features available in vector architectures. The VA4EE 2018 workshop will be a meeting point for vector architecture researchers, covering the full development stack, from applications to hardware.
VA4EE 2018 is organized in conjunction with The 47th International Conference on Parallel Processing (ICPP 2018), Eugene, Oregon, USA during August 13-16, 2018.
Topics of interest, of both theoretical and practical significance, include but are not limited to vector
- Programming framework
- Programming model and language explorations
- Compilation and optimization including algorithmic improvements and code optimization
- Performance Analysis and Debugging Tools
- Performance Metrics and Evaluations
- Libraries and run-time systems
- Design, generation, verification and validation of representative applications
- Case-studies of representative applications
- Innovative applications for vector architectures
- Hardware studies and micro-architectural implementation tradeoffs
The goal of the workshop is to present the attendees with novel hardware enhancements, vectorization tools, codes and strategies as well as current (and future) trends and in vector architectures.
Important Dates
Submission due date: April 13, 2018- Submission due date: April 20, 2018
- Notification date: May 4, 2018
- Camera Ready due date: May 31, 2018
- Author registration due date: TBA
- VA4EE Workshop date: August 13, 2018
- ICPP Conference dates: August 13-16, 2018
Submission Guidelines
Submitted papers must not have appeared in or be under review/consideration for another workshop, conference or a journal during the review process. Paper reviews will be single-blind so please include author names in your submission. Authors are requested to follow the ACM sigconf template (as specified at the ICPP webpage http://oaciss.uoregon.edu/icpp18/index.php).
Please submit regular full papers (6 to 8 pages) including all figures, tables, and references. Papers should be submitted electronically in PDF format together with a short abstract (approximately 150 words) using the EasyChair Submission system, following the link:
https://easychair.org/conferences/?conf=va4ee2018
Special issue in Journal of Supercomputing (JCR-Q2)
Selected papers will be invited to submit to a special issue on Vector Architectures and Applications in the Exascale Era for the Journal of Supercomputing.
General Chairs
- Juan M. Cebrian, Barcelona Supercomputing Center
- Magnus Själander, Norwegian University of Science and Technology
Program Committee
- Alberto Ros, University of Murcia
- Alexandra Jimborean, Uppsala University
- Rakesh Kumar, Uppsala University
- Magnus Jahre, Norwegian University of Science and Technology
- Nikita Nikitin, Staff Engineer at Mentor Graphics
- Pavlos Petoumenos, University of Edinburgh
