Welcome to the companion website for The UVM Primer. I created this website because I know that it takes more than a book, even a most excellent book, to really learn a new technology such as the Universal Verification Methodology. www.theuvmprimer.com provides you with additional resources to give you a better feel for using the UVM:
I hope the resources on this website help you learn the UVM quickly and I look forward to meeting you on the Facebook group.
The UVM Primer teaches by creating a testbench for a simple design, the TinyALU. We learn the UVM by slowly converting the TinyALU testbench from a single-use SystemVerilog testbench into an object-oriented UVM testbench.
The UVM Primer Channel on Youtube examines each of the intermediate testbenches, explaining the new features in each testbench and giving you a detailed description of how each testbench works.
All the examples in The UVM Primer have been compiled and tested. You can download the code, sorted by chapter, and run the examples yourself. They also make handy tools to remind you of syntax later.
There are two excellent ways to learn a new technical skill:
The UVM Primer Google Group allows you to do both. I will be on the group along with other engineers who are either learning the UVM or helping others learn the UVM. Come join the conversation.
If you're a Facebook person (like me) you might want to like the UVM Primer page on Facebook. I'll be sharing highlights of the videos and discussions on the other pages.
The UVM Primer is a step-by-step introduction to the Universal Verification methodology. Using a simple device under test, the TinyALU, we create a testbench in SystemVerilog. Then, chapter-by-chapter and step-by-step, we convert the SystemVerilog testbench into a full blown UVM Testbench. Over the course of this transformation, you'll learn the following concepts:
By the end of The UVM Primer you will be able to contribute to a UVM-based verification project.