The UVM Primer
Welcome to the UVM Primer Online
Welcome to the companion website for The UVM Primer. I created this website because I know that it takes more than a book, even a most excellent book, to really learn a new technology such as the Universal Verification Methodology. www.theuvmprimer.com provides you with additional resources to give you a better feel for using the UVM:
- Example Code—The best way to learn a new programming technique is to edit and run actual code. The UVM Primer has hundreds of code examples (190 actually) in its pages and you can download all those code examples from this website.
- Code Videos—Technical books about coding must always balance the need for line-by-line code explanations with the need to keep the narrative moving. Gloss over the code too much and readers get disconnected from what's really happening, but dwell on each line too long and readers lose the big picture. The UVM Primer addresses this challenge by focusing on the concepts illustrated by the code and leaving the line-by-line descriptions of the code to Youtube videos.
- Questions and Answers—Sometimes nothing beats asking the author “What did you mean when you wrote this?” You can talk to me and other UVM users on The UVM Primer Facebook Group
I hope the resources on this website help you learn the UVM quickly and I look forward to meeting you on the Facebook group.
The Example Code Explained on Youtube
The UVM Primer teaches by creating a testbench for a simple design, the TinyALU. We learn the UVM by slowly converting the TinyALU testbench from a single-use SystemVerilog testbench into an object-oriented UVM testbench.
The UVM Primer Channel on Youtube examines each of the intermediate testbenches, explaining the new features in each testbench and giving you a detailed description of how each testbench works.
Ask Questions, Get Answers
There are two excellent ways to learn a new technical skill:
- Ask a great question.
- Answer a great question.
The UVM Primer Google Group allows you to do both. I will be on the group along with other engineers who are either learning the UVM or helping others learn the UVM. Come join the conversation.
The UVM Primer is a step-by-step introduction to the Universal Verification methodology. Using a simple device under test, the TinyALU, we create a testbench in SystemVerilog. Then, chapter-by-chapter and step-by-step, we convert the SystemVerilog testbench into a full blown UVM Testbench. Over the course of this transformation, you'll learn the following concepts:
- Object-oriented Programming
- Object-oriented Testbench Design
- UVM Tests
- UVM Components
- UVM Communication with Ports
- UVM Configuration
- UVM Agents
- UVM Sequences
By the end of The UVM Primer you will be able to contribute to a UVM-based verification project.