Agenda

AMAZE: Accelerated MiMC Hardware Architecture for Zero-Knowledge Applications on the Edge

An Extensive Study of Flexible Design Methods for the Number Theoretic Transform

High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves

EmMark: Robust Watermarks for IP Protection of Embedded Quantized Large Language Models

Mind the Portability: A Warrior's Guide through Realistic Profiled Side-channel Analysis

VALIANT: An EDA Tool Flow for Side-Channel Leakage Evaluation and Tailored Protection

Strength in numbers: Improving generalization with ensembles in machine learning-based profiled side-channel analysis

RTL2MμPATH: Multi-μPATH Synthesis with Applications to Hardware Security Verification

Maya: Using Formal Control to Obfuscate Power Side Channels

Defending Cryptographic Code from Spectres on Existing Hardware with Software-Compiler-Hardware Codesign

Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques

The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks

RowPress: Amplifying Read Disturbance in Modern DRAM Chips

SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation

LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs

Pentimento: Data Remanence in Cloud FPGAs

Silicon Validation of LUT-based Logic-Locked IP Cores

Security Verification of the OpenTitan Hardware Root of Trust