NIC25: Neuromorphic integrated circuits 

Goals

The topic area will explore novel neuromorphic architectures, circuits and hardware that could demonstrate neurmorphic performance advantage for sensing and computing when compared to other architectures that use conventional analog-to-digital converters (ADCs), central processing units (CPUs), graphical processing units (GPUs) and quantum processors. 

Specifically we will focus on problems where the neurmorphic advantage can be clearly demonstrated which include: 

• event-based sensing and perception, 

• combinatorial optimization, 

• stochastic simulations, 

• artificial intelligence-based workloads, 

• and closed-loop dynamical system and control problems. 

The topic area participants will delve into the architecture of current neuromorphic hardware and into concepts like event-based sensing and processing, compute-in-memory and in-sensor compute, asynchronous computing and Monte-Carlo sampling. The participants will also explore synergies between the optimization techniques and the dynamics that can naturally mapped onto neuromorphic devices, circuits and systems. Using behavioral simulations, circuit simulations and FPGA-based emulation platforms, the participants will evaluate the performance of these approaches to the current state-of-the-art benchmark tasks.

Projects

1. Benchmarking and testing of neuromorphic circuits and systems

2. Neuromorphic vision sensors and processors

3. Neuromorphic audition sensors and processors

4. Neuromorphic olfaction sensors and processors

5. Neuromorphic tactile sensors and processors

6. Other neuromorphic sensors (EEG, LIDAR, etc.)

Materials, Equipment, and Tutorials:

The participants will have access to open-source process design kits (PDKs) for IC design and software models that can emulate different neuromorphic architectures. We will have three threads in which participants can engage with IC design projects with increasing degree of complexity: (a) Basic Digital VLSI, where workshop participants can learn how to create their own simple digital designs and run it through synthesis using a set of GitHub actions that automates the synthesis process in an open-source flow; (b) Advanced Digital VLSI, where commercial tools will be used for advanced, larger scale designs, where participants can design their own IP blocks that can be integrated at or after the end of the workshop; (c) Asynchronous design and mixed-signal design optimizations of memory-centric architectures that can be used to accelerate neuromorphic algorithms.

The following commercial-off-the-shelf (COTS) hardware platforms and software packages will be used by the topic area participants for testing and benchmarking:

1. FPGA hardware and software emulation platform -- for testing and demonstrating neuromorphic ICs.

2. Cloud-based hardware emulation platform  -- for large-scale simulation and implementation of the neuromorphic optimizers.

3. Open Cloud Simulation -- for ASIC design and simulation.

Dockers with pre-installed EDA tools will be provided to students to enable them to focus on design and testing over debugging and installation.

Hardware Tutorials:

• Digital Design Guide with Tiny TapeOut

• Open-Source Silicon Interactive Tutorials

• eFabless Open MPW Walkthrough Video

Preparation material, literature:

Designing SNN accelerators using open silicon: 

F. Modaresi, M. Guthaus, J. K. Eshraghian, "OpenSpike: An OpenRAM SNN Accelerator", 2023 IEEE International Symposium on Circuits and Systems (ISCAS), May 2023. [arXiv]

Online Learning On-Chip at 28-nm:

C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm2 task-agnostic spiking recurrent neural network processor enabling on-chip learning over second-long timescales", 2022 IEEE International Solid-State Circuits Conference (ISSCC), Feb 2022. [IEEE]