FAQ

FAQ

Frequently Asked Questions

  • Q: What is DCTK

A: DCTK (i.e. Delay Calculator Took Kit) is code infrastructure created to develop delay calculator. The source code is available at https://github.com/geochrist/dctk

  • Q: Does computed delay need to be propagated to next level of logic?

A: No. For this contest, participants need to compute delay of one stage only. Using look up table of library model and test circuit generated by DCTK, students need to implement their algorithm of delay computation.

  • Q: What type of input of slew rate should be used for cell delay computation?

A: For this contest, ramp type of input slew was used in earlier version of DCTK. From the Jan 2020 , DCTK is constructing waveform of driver input using value of "normalized_driver_waveform" from standard cell library.

  • Q: In the code of DCTK in file "/test/runme", there is something called "pimodels." What happens if that option is enabled?

.A: That option is used to generate RC netlist using pimodels .

  • Q: In code of DCTK in file /src/delay_calc_tool.cpp, at line 165, a variable called "compute_delay_retval". The same line makes a call to computer_delays() in delay_calculator.cpp. Is it just an integer for evaluating whether there was an error?

A: Yes, compute_delay_retval is for determining if there is an error.

  • Q: Can you share information on 7 nm open source library model from Arizona State University (i.e ASU)?

A: TAU contest committee is coordinating with ASU to generate current source model for thier open source library of 7nm.

Contestants can download library of ASU from http://asap.asu.edu/asap/ after registering with their university email account.

  • Q: After downloading ASU library from where can get CCS model, Spice model of process technology and spice netlist of library cells?

A: In 1.6 version of ASU library location of CCS model, technology model and spice netlists are as follows

<my_dir>/lib_release_191006/asap7_7p5t_library/rev25/LIB/CCS/*.lib.gz ( current source model of library)

<my_dir>/ asap7PDK_r1p6/models/hspice/7nm_TT.pm ( Technology model of 7 nm)

<my_dir>/lib_release_191006/asap7_7p5t_library/rev25/CDL/xAct3D_extracted/Extracted_netlists/*.sp ( Spice netlist of Library cells)

  • Q: Do we need to post-process CCS model of ASU library to use them with DCTK?

A: Yes. CCS model of 1.6 version of ASU library has incorrect syntax for pre-driver waveform & normalized_driver_waveform. User need to delete using below commands

"

mv asap7sc7p5t_INVBUF_RVT_TT_ccs_191031.lib asap7sc7p5t_INVBUF_RVT_TT_ccs_191031.lib_org

sed '/waveform_time_template/,/\}/d;/^\s*driver_waveform/d;' asap7sc7p5t_INVBUF_RVT_TT_ccs_191031.lib > tmpLib

mv tmpLib asap7sc7p5t_INVBUF_RVT_TT_ccs_191031.lib

"

  • Q: After post-processing CCS model of ASU, we are getting error of insignificant digit from Liberty Parser. Can we ignore the error?

A: Yes, user can ignore below ERROR

ERROR: The vector 'values' attribute contains XXXX, which has less than X digits of precision. (Semantic Error found in data.)

ERROR: The vector 'values' attribute contains one or more zero values. (Semantic Error found in data.)

  • Q: Can contestants modify data structure of reading Liberty or SPEF of DCTK?

A: NO. Contestants should put effort in writing the delay calculation engine ("compute_delays" method). Contestants can re-organizing the data for best performance (memory/runtime) within sub-routine of "compute_delay". They should perform in-memory transformation, taking the structure that has been read in by the included parsing code. Various options are available, including deriving new objects from the provided classes to store data in the different formats. Or perhaps create all new classes for different data organization. Original classes SHOULD NOT be modified as submitted code/libraries must link with the baseline, for testing purposes.

  • Q: Which part of the code will be evaluated? Is only "compute_delays" method to be evaluated?

A: Yes, only the compute_delays portion of the code will be benchmarked for runtime and memory. Modifications for other portions of the code are not allowed, unless contest committee deem it good for everyone.

  • Q: Do contestant need to take care of side load pin of multi-input cells and non-unate timing arc?

A: In this contest, we are focusing ONLY celll delay and output slew of inverters and buffers. This will remove the requirement to correctly sensitize any side-loads and delay computation of non-unate arc like XOR cell. Participant should spend majority of their time in delay calculation algorithm by interpreting current look-up table of liberty models.

  • Q: Do we have any timing model that contain only Inverter and Buffers?

A: YES. Library from ASU provides timing model of Inverter & Buffers only. Please download their library from http://asap.asu.edu/asap/ .

  • Q: From where can contestants find an example circuit ?

A: The example circuits are YAML file that are generated through DCTK. Contest committee will use similar circuit and do spice simulation to check the result of all solution.

  • Q: How do contestants validate their result ?

A: To validate result, participants need to run spice simulation for the a circuit that describe in YAML file.

Right now contestants need to write spice netlist & stimulus for any circuit manually, In near future we will enhance DCTK to generate spice netlist of a circuit along with YAML.

  • Q: What is expected precision for the computed delay (i.e. +/- 1ps or +/-5%)

A: Accepted precision of the output will be +/- 5% & +/- 2 ps against spice result for cell delay and +/-10% & +/- 4ps against spice result for slew.