Welcome to the HDL Laboratory course
Place: ECE Simulation lab/Admin block, NITPY
Class timings: Fri- 9.00pm-12.00pm
Teaching Assistants: Ms. Jayanthi, Ph.D Scholar, Mr. K Praveen Kumar, Ph.D Scholar.
Introduction to Verilog HDL, sample code, and demonstration of the simulation tool - click here for the materials
Verilog HDL basics - an introduction video lecture from the Intel team - click here
Demonstration video to run Verilog codes and verify truth table/timing diagrams on Qucsstudio simulator-click here
(One-week deadline for every experiment submission)
(Week-01) Introduction to HDL, Verilog basics with examples of basic logic gates and introduction to FPGA
(Week-02) Exp1-Adders
(Week-03) Exp2-Subtractors
(Week-04) Exp3-Multiplexers and Demultiplexers
(Week-05) Exp4-Encoders
(Week-06) Exp5-Code converters and Decoders
(Week-07) Exp6- Multipliers
(Week-08) Exp7-Flipflops
(Week-09) Exp8-Counters
(Week-10) Exp9-Shift registers
(Week-11) Exp10-Moore & Mealy Finite-State-Machines