EC657/HDL Laboratory (I-year M.Tech VLSI)
EC657/HDL Laboratory (I-year M.Tech VLSI)
Welcome to the HDL Laboratory course
Place: ECE Simulation lab/Admin block, NITPY
Class timings: Fri- 01.30pm-4.30pm
Teaching Assistant: Ms. Jayanthi, Ph.D Scholar, NITPY
Attendance sheet - Class representative may fill it! Others can view it!
Introduction to Verilog HDL and demonstration of the simulation tool - click here for the materials
Verilog HDL basics - an introduction video lecture from the Intel team - click here
(One-week deadline for every experiment submission)
(Week-01)
(Week-02)
(Week-03) Exp1-Adders and Subtractors
(Week-04) Exp2-Multiplexers and Demultiplexers
(Week-05) Exp3-Encoders and Decoders
(Week-06) Exp4-Code converters
(Week-07) Exp5-Flipflops