EC312/VLSI Design Lab (III-year B.Tech ECE)

NEW!!! Download the front page, index page, and a sample experiment format for the VLSI lab record - click here

Introduction to Verilog HDL and demonstration of the simulation tool - click here for the materials

Verilog HDL basics - an introduction video lecture from the Intel team - click here

Download the sample record work of an experiment here.

Demonstration video to run Verilog codes and verify truth table/timing diagrams on Qucsstudio simulator-click here

List of Experiments

(One-week deadline for every experiment submission)

(Week-01) Implementation of Adders & Subtractors using Verilog HDL

(Week-02) Implementation of MUX and DEMUX using Verilog HDL

(Week-03) Implementation of Encoder and Decoder using Verilog HDL

(Week -04) Implementation of Flip-Flops using Verilog HDL

(Week -05) Implementation of Counters using Verilog HDL

(Week-06) Simulating n-MOSFET and p-MOSFET characteristics using SPICE (demo video)

(Week-07) Voltage Transfer Characteristics (VTC) simulation of a CMOS inverter (demo video)

(Week-08) Implementation of universal shift register

(Week-09) Implementation of Finite State Machine (FSM)

(Week-10) Simulating transient behavior of gates at the transistor level using SPICE