Project: “Development of Anti-jamming and Anti-Spoofing baseband signal processing algorithms for GNSS receiver provisioned UAVs”
Post (1): Senior Research Fellow/ Senior Project Associate, (Monthly Emolument: 49,560/-)
Full-time PhD: One position
Hardware: Xilinx z7020 FPGA SoC with AD9361 RF front end will be procured and used.
Software: Vivado-SDK tool will be used for the development of the FPGA IPs and embedded software.
Streaming transceiver for sine wave will be developed first followed by the development of Modulator-Demodulator IPs.
Embedded software will be then developed for data handling.
Python-based streaming software will be developed for demonstration purpose.
Student/staff team: Mr. Dhruv Shah
This technology is being developed for precision ranging among nodes using ultrasonic Tx Rx module and GPS timing information. In this technique, time stamp of ultrasonic signal transmission is shared to all recipient nodes listening ultrasonic signal. The local time of all nodes is synchronized to GPS timing. This precise timing information is used to compute time of travel of ultrasonic signal between transmitting and receiving nodes. Using the time of travel and sound velocity, distance among nodes in sub-centimeter accuracy is computed. The computed distance can be used for formation of compact swarm.
Student/staff team: Mr. Rinkesh Patel, Mr. Aksh Patel
Around Xilinx z7020 SoC and NT1068.2 RF Front-end for Multiband GNSS and AD9361 RF front end for Communication, this R&D activity aims at development of highly configurable custom SDR-cum-GNSS receiver.
This research activity aims at developing base band GNSS signal processing algorithms to estimate attitude of spinning projectiles
Student Team: Divy Prakash Mishra, PhD Scholar
This research activity aims at developing base band GNSS signal processing algorithms a MIMO GNSS receiver with anti-jamming and anti-spoofing capability.
Zynq z706/z7030 boards with AD-FMCOMMS5 RF front ends comprising 4x4 MIMO and NT1068.2 4 channel are being used along with required RF chain components for experiments.
MATLAB and Python is being used for post processing of signal.
FPGA SoC programming aims at real time signal signal processing in its future scope
Student Team: Rita Choudhary, Aman Varshney, Divy Prakash Mishra, PhD scholars, ECE
This development carried out development of an autonomous pesticide spraying robot which can navigate autonomously using image processing, range sensors, and inertial sensors and can autonomously detect infected plants and spray controlled pesticides using AI/ML techniques.
The project won level-2 funding (total 1,50,000) for PoC in GUJCOST Robofest 3.0.
Student Team: Hardik Chaudhary, Vardan Mittal, Pratham Sharma, Pratham Parmar, Aaditya Nimkar, B-Tech, MED.
This development carried out fabrication and testing of low cost hardware for RF power transmission with initial prototype for 100 meters range.
The project secured PoC funding from SSIP 2.0, Government of Gujarat.
Student Team: Vedant Arya, B-Tech, EE