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Ongoing Research Projects
Custom Hardware and Embedded/Cyber-Physical System Design for Privacy-Preserving Applications
FPGA-based accelerators for fully homomorphic encryption primitives
Developing real-world privacy-preserving applications using homomorphic encryption
Sponsors: RIT SURF (2024), RIT FEAD (2024), NSF CRII (2023-2025, 2 years), IITP (2020-2023, 4 years), and UW RRF (2020-2021, 1 year)
Collaborators: Altera, Seoul National University, and Inha University
Publications: [ReConFig'19], [FCCM'20], [RTCSA'21], [GLSVLSI'22], [MMSP'22-1], [MMSP'22-2], [ISCAS'23-1], [GLSVLSI'24], [ESL'25], [MWSCAS'25], [Asilomar'25], [WDSFPGA'26], [DATE'26], and [FPT'26]
Custom Hardware Design for Approximate Arithmetic
FPGA-based accelerators for approximate operations on real numbers
Publications: [GLSVLSI'19], [ISCAS'21], [ISCAS'23-2], [GLSVLSI'23], and [TVLSI'24]
Sensor Systems for Robotics
Design and optimization of lightweight camera-based depth estimation algorithms
Sponsor: NY SMART I-Corridor Tech Hub NY THRIVE (2026-2027, 1 year)
Collaborator: Oculi
Past Research Projects
Custom Hardware Design for Machine Learning Problems
FPGA-based accelerators of binary convolutional neural networks
Publication: [FCCM'18]
Management on Non-Volatile Memory Systems
Hot address-based wear-leveling for phase-change memory
Sponsor: SK Hynix (2016-2017)
Publications: [CAL'19] and two patents
Fast and Energy-Efficient RGBW Display Systems
Look-up table and interpolation-based RGB-to-RGBW conversion
Publications: [APCCAS'16] and [TCAS-II’18]
Custom Hardware Design for Image/Video Processing
Hardware accelerators for frame memory compression
Sponsors: LG Display (2012-2015), ETRI (2015-2016)
Publications: [Displays'15], [TMM'16], [TCE'16], [JDT'16], [ISCAS'16], [JETCAS'16], [JSTS'17-1], and [JSTS'17-2]
Cost-Effective Computer Vision Algorithms
Gesture recognition-based virtual keyboard system
Trajectory detection using pedestrian and surrounding information
Face detection and tracking using H.264/AVC information
Publications: [ICEIC'12], [SPC'16], and [THMS'22]
Acknowledgement
Grateful to the National Science Foundation (NSF), NY SMART I-Corridor Tech Hub, Institute for Information and Communications Technology Promotion (IITP), University of Washington Royalty Research Fund (RRF) program, and Rochester Institute of Technology Faculty Education and Development (FEAD) and Summer Undergraduate Research Fellowships (SURF) programs for the funds
Grateful to Altera (Intel) and AMD-Xilinx for their FPGA donations and collaboration opportunities
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