Nanoscale Devices, VLSI Circuit & System Design Lab

Indian Institute of Technology Indore


Sumiran Mehra

MS Research Scholar, IIT Indore

Indian Institute of Technology, Indore

Email: ms2004102007@iiti.ac.in / 1296sumi@gmail.com

LinkedIn: https://www.linkedin.com/in/sumiran-mehra

MS Research Thesis :

Topic: Enhanced Performance Hardware Efficient Architecture for SoftmaxFunction in Deep Learning

Advisor: Dr. Santosh Kumar Vishvakarma

About Project: Deep Neural Network(DNN) is widely used in computer vision, natural language processing, image recognition and edge AI based IOT application. Current DNN models such as AlexNet, ResNet, or LeNet have been using Softmax activation function at its classification layer, also advanced neural network coprocessors such as Transformer and Capsule network have been using SF at its hidden layers. However for high throughput, DNN uses parallel computational blocks which comes with area overhead. In this work, we designed performance centric, area efficient Softmax Function(SF) design using CORDIC architecture. The inference accuracy is tested using python and design is implemented using HDL on Zybo. Further, the design is validated for ASIC and postsynthesis results at 45nm technology node shows better performance com-pared to previous works.

Research Interests :

  1. FPGA

Title: Reading and Writing to SD Card Implementation

Work: In this work, an image is saved in SD Card and saved image isloaded to the DNN model as an input feature. The operation is performed Xilinx Vivado Hlx development tool using on Zynq FPGA board.

Tools: Vivado Hlx, SDK, Simulink

  1. RTL to GDSII

Title: Softmax Function implementation

Work: Softmax Function synthesis and verification of functionality using Design Compiler Formality. Encounter, used for planning, placing,and routing. Full ASIC design flow is performed under this work at 180nm technology node.

Tools: Synopsis-Design Vision, Formality, Encounter, Primetime.

  1. Custom CMOS Design

Title: 6T-SRAM cell Design

Work: Design of SRAM (Schematic and Layout), postlayout simulationand verification, result extraction (Read, Write, and Hold operation).

Tools: Cadence-Virtuoso, Calibre, Spectre

  1. PCB Design

Title: Touch Sensor using Darlington pairWork:A 5V-10V variable power supply has been made and used topower a touch sensor implemented using darlington pair.

Software Skills :

Verilog HDL, Python, Matlab, Prog. Language - C, Micro Processor (8085/8086), LATEX

Publications :

  1. Sumiran Mehra, Shaurya Deep Singh, Subhangini Kumari, S.V. Karatangi, Reshu Agarwal and Amrita Rai,‘Design and Implementation of Self-Defence Device for WomenSafety’,International Conference on Artificial Intelligence, advances and applications,2019.

  2. Sumiran Mehra, et al., ‘Enhanced Performance Hardware Efficient Architecture for Softmax Function in Deep Learning’ (About to submit)

Achievements :

March 2020 GATE: Score-580 AIR-2425 with 97 percentile