Book Chapter:
S. Agarwal, and H.K. Kapoor, "Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques" VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, Springer, Vol. 500, Chapter 3, pp. 46-71, 2019. (Selected Papers)
Journals:
S. Agarwal, and H.K. Kapoor, "Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 26, no. 10, pp. 1881-1894, Oct. 2018.
S. Agarwal, and H.K. Kapoor, "Improving the Lifetime of Non-Volatile Cache by Write Restriction" in IEEE Transactions on Computers (TC), vol. 68, no. 9, pp. 1297-1312, 1 Sept. 2019.
A. Nath, S. Agarwal, and H. K. Kapoor, "Reuse Distance based Victim Cache for Effective Utilization of Hybrid Main Memory System" in ACM Transactions on Design Automation of Electronic Systems (TODAES), 25 (3), Article 24, May 2020.
S. Agarwal, and H.K. Kapoor, "Improving the Performance of Hybrid Caches Using Partitioned Victim Caching" in ACM Transactions on Embedded Computing Systems (TECS), 20(1), Article 5, December 2020.
S. Saha, S. Chakraborty, S. Agarwal, R. Gangopadhyay, M. Själander and K. McDonald-Maier, "DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore," in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 34, no. 2, pp. 718-733, Feb. 2023.
A. Goens, S. Chakraborty, S. Sarkar, S. Agarwal, N. Oswald, V. Nagarajan, “Compound Memory Models” In Proceedings of the 44th ACM SIGPLAN International Conference on Programming Language Design and Implementation (PLDI'23), pp. 1-20, 2023, Orlando, USA.
S. Saha, S. Chakraborty, S. Agarwal, M. Själander and K. McDonald-Maier, "ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 10, pp. 2944-2957, Oct. 2024.
S. Chakraborty, T. Bunnam, J. Arunruerk, S. Agarwal, S. Yu, R. Shafik, M. Själander, "HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM based Caches", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025. (Accepted)
S. Saha*, S. Chakraborty*, S. Agarwal*, M. Själander and K. McDonald-Maier, "PRECIOUS: Approximate Real-Time Computing in MLC-MRAM based Heterogeneous CMPs", in IEEE Transactions on Computers (TC), 2025. (*Contributed Equally) (Accepted)
Conferences:
S. Agarwal, S. Chakraborty and M. Sjlander, "TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture" In 38th IEEE International Parallel & Distributed Processing Symposium (IPDPS'24), pp. 852-864, 2024, San Francisco, USA.
S. Agarwal, S. Chakraborty and M. Sjlander, "Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)” In Proceedings of the 60th ACM/IEEE Design Automation Conference (DAC'23), pp. 1-6, 2023, San Francisco, USA.
S.Agarwal and S.Chakraborty, "ABACa: "Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache" In 32nd IEEE International Conference on Application-Specific Array Processors (ASAP'21), Virtual Conference, 2021.
M. Baranwal, U. Chugh, S. Dalal, S. Agarwal and H. K. Kapoor, "DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches" In 22nd International Symposium on Quality Electronic Design (ISQED'21), Virtual Conference, California, USA, 2021, pp. 469-475.
K. Rani, S. Agarwal, and H. K. Kapoor, "DidaSel: Dirty data based Selection of VC for effective utilization of NVM Buffers in On-Chip Interconnects" In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '20), Boston USA, 2020, pp. 151-156.
S. Agarwal, and H. K. Kapoor, "LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors" 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020, pp. 194-199.
S. Agarwal, and H. K. Kapoor, "Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction" In Proceedings of the 2019 on Great Lakes Symposium on VLSI (GLSVLSI '19), Washington, USA, 2019, pp. 213-218.
S.S. Manohar, S. Agarwal, and H. K. Kapoor, "Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks" In Proceedings of the 2019 on Great Lakes Symposium on VLSI (GLSVLSI '19), Washington, USA, 2019, pp. 225-230.
K. Rani, S. Agarwal, and H. K. Kapoor, "Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon," 2018 8th International Symposium on Embedded Computing and System Design (ISED), Cochin, India, 2018, pp. 74-79. (Best Paper Award)
A. Kulkarni, C. Joshi, K. Rani, S. Agarwal, S. P. Mahajan, and H. K. Kapoor, "Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors," 2018 8th International Symposium on Embedded Computing and System Design (ISED), Cochin, India, 2018, pp. 230-235.
A. Kulkarni, K. Rani, S. Agarwal, S. P. Mahajan, and H. K. Kapoor, "Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors," 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Hyderabad, India, 2018, pp. 52-57.
S. Priya, S. Agarwal, and H. K. Kapoor, "Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets," 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, India, 2018, pp. 457-458.
S. Agarwal, and H. K. Kapoor, "Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets," 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Abu Dhabi, UAE, 2017, pp. 1-6. (Best Paper Award)
S. Agarwal, and H. K. Kapoor, "Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors," 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 29-34.
S. Agarwal, and H. K. Kapoor, "Restricting writes for energy-efficient hybrid cache in multi-core architectures," 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, 2016, pp. 1-6.
S. Agarwal, and H. K. Kapoor, "Towards a dynamic associativity enabled write prediction based hybrid cache," 2016 20th International Symposium on VLSI Design and Test (VDAT), Guwahati, 2016, pp. 1-6.