Embedded Files
晶片設計 (Integrated Circuit Design)
晶片設計 (Integrated Circuit Design)
1. 可單階或多階操作之高速讀寫1Kb 電阻式記憶體之最佳設計 (IEEE Symposium on VLSI 2009 論文及IEEE design and test of computer 期刊刊登)︰研究開發創新之寫入與讀取電路，開發高性能RRAM macro，經實測寫入時間只需5ns，讀取時間只需8.5ns，此外亦開發RRAM第一個MLC讀寫電路，為當時全世界第一顆RRAM晶片。
2. 讀取速度7.2ns多階驗證寫入速度160ns之4百萬位元電阻式記憶體晶片 (IEEE ISSCC 2011 論文刊登)︰帶領工研院研發團隊與清大張孟凡教授團隊共同開發，研究創新使用動態箝制偏壓讀取方法，由負回授放大器隨著資料線/位元線(DL/BL)的電壓變化而產生，此操作行為能夠增加位元線充電電流，加速操作，並開發出RRAM 4-Mb macro，為國際上第一顆M bits RRAM macro。 經過實際量測，寫入可於5ns內完成，讀取可於7.2ns內完成，為當時全世界最大容量，操作速度最快的RRAM晶片。
3. 解決over-RESET造成sensing margin降低的問題(刊登於IEICE 期刊 2012 .6，同時美國、台灣專利均已獲證)︰研究突破創新開發Write-resistance tracking scheme，當RRAM電阻已完成轉態時，即關掉寫入電壓。與傳統的寫入驗證方法相比除了可節省58%能量消耗外，亦解決over-RESET問題，增加sensing margin。
4. 應用於IoT 低功耗之7T2R 非揮發性靜態隨機存取記憶體 (IEEE ASSCC 2013 論文刊登)︰為了應用於IoT物聯網低功耗需求，開發以RRAM 元件與SRAM cell進行3D 整合之非揮發性靜態隨機存取記憶體(non-volatile SRAM, nvSRAM)。此架構在正常工作模式下為使用6T SRAM，而在待機模式下，資料將儲存至RRAM中，達到零待機功率消耗的目的。此架構使用7顆電晶體與2個RRAM元件所完成，與6T SRAM及6T2R nvSRAM相比，其write margin可改善1.03倍及1.37倍。其功率消耗亦低於8T2R nvSRAM。VDDmin及存取時間分別為0.7V及8.3ns。
This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 mm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.
5. 適用於IMC (In-Memory Computing)之可重編式非揮發性查找表 (IEEE ASSCC 2014 論文刊登)︰為了應用於人工智慧、類神經運算等下世代運算技術，開發適用於記憶體內運算IMC之架構。以RRAM 元件與邏輯電路相整合，完成各種邏輯閘，並實際完成晶片驗證。此架構與SRAM-MRAM hybrid 二輸入之LUT(Look-Up Table)相比，面積節省79%以上，而與MRAM完成的二輸入LUT相比，亦節省11.5%。，經過量測後，其delay time為0.9ns。
This study demonstrated a nonvolatile look-up table (nvLUT) that involves using resistive random access memory (ReRAM) cells with normally-off and instant-on functions for suppressing standby current. Compared with the conventional static random access memory (SRAM)- magnetoresistive random-access memory (MRAM)-hybrid LUTs, the proposed ReRAM-based two-input nvLUT circuit decreases the number of transistors and the area of nvLUT by 79% and 90.4%, respectively. The areas of the two- and three-input ReRAM nvLUTs are 11.5% and 74.2% smaller than the other MRAM-based two-input and PCM-based three-input LUTs, respectively. Because of the low current switching and high R-ratio characteristics of ReRAM, the proposed ReRAM-based nvLUT achieves 24% less power consumption than that of SRAM-MRAM-hybrid LUTs. The functionality of the fabricated adder of the three-input ReRAM nvLUT was confirmed using an HfOx-based ReRAM and a 0.18-μm complementary metal-oxide semiconductor with a delay time of 900 ps.
應用系統 (Application System)
應用系統 (Application System)
1.開發應用於物聯網之感測器系統平台︰(2016資訊月百大創新產品獎)
帶領工研院團隊開發感測器系統應用平台，其可配合不同之感測器與演算法，就可以成為新的應用產品。其技術特色如下：
a.於可撓曲之基板完成電路系統
b.使用可撓式薄型電池,在60 x 20 x 3mm3的體積下，達到320mAh的容量
c.即時的資料分析與回饋，針對應用情境進行分析開發其演算法、在接收到感測器的資料後，可以即時在感測標籤進行運算，如運算結果需要回報，再進一步傳輸至android 裝置而使用者可以在裝置上決定接下來要如何處理。
Google Sites
Report abuse