Dol Sohn

Education

• B.S. School of Electronic Engineering, Chungbuk National University, Republic of Korea.  Mar. 2019 - Feb. 2025 (GPA : 4.19 / 4.5)

• M.S.  School of Semiconductor Engineering, Chungbuk National University, Republic of Korea. Mar. 2025 - Present (B.S. and M.S. Integrated)

Research Interest

• Memory (DRAM cell), Logic Device (GAA/Nanosheet FET) 

• Device Design, Simulation & Validation 

• Plasma Enhanced Fabrication Processes 

Technical Proficiency 

Software Proficiency 

• EDA Tools : Synopsys Sentaurus, Ansys (Icepack, HFSS)

• Data Analysis : Python

Fabrication Equipment Proficiency 

• Reactive Ion Etcher, VITA 8 / Produced by Femto Science 

• Sputter, DDHT-DS3HR4 / Produced by Daedong Hightech

• Mask Aligner / Spin Coater, MA-6 / Produced by Karl Suss

• Thermal Evaporator, KVE-EG / Produced by Korea Vaccum Tech 

• Thermal Deuterium Annealing (LTDA) / Custom-Made

• Rapid Deuterium Annealing (RDA) / Custom-Made

Device Characterization Proficiency 

• Device Parameter Analyzer, Keithley 4200A-SCS / Produced by Keithley

• Device Parameter Analyzer, B1500A / Produced by Keysight

• Probe Station, MS-8000 / Produced by MS Tech

Publications(SCIE)

• D. Sohn, M.-K. Lee, D.-E. Bang, H.-J. Park, E.-C. Yun, S.-M. Kang, M.-W. Kim, H. Jeon*, and J.-Y. Park*, "Wrap-Around Word-Line DRAM Cell Transistor Enabling Enhanced Read/Write Speed", IEEE Trans. Electron Devices, vol. xx, no. x,  pp. xxxx-xxxx, in press.
  [ Website ]  

• D. Sohn, M.-K. Lee, J.-W. Yeon, M.-W. Kim, T.-H. Kil, E.-C. Yun, H.-J. Park, and J.-Y. Park*, "V-Notch Shaped Contact Design in Nanosheet FETs for Enhancing Chip Performance", IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. xx, no. x,  pp. xxxx-xxxx, in press. [ Website ]

• H.-J. Park, M.-K. Lee, E.-C. Yun, D. Sohn, M.-W. Kim, S.-M. Kang, H. Jeon, and J.-Y. Park*, "Investigation of Inner Spacer-Less Nanosheet FETs from an Off-State Current Perspective", IEEE Access, vol. 13, pp. 199876-199882, Nov. 2025. [ Website ] 

• E.-C. Yun, H.-J. Park, M.-K. Lee, T.-H. Kil, J.-W. Yeon, M.-W. Kim, D. Sohn, and J.-Y. Park*, "Demonstration of Rapid Deuterium Annealing for High-Performance MOSFETs with Reduced Thermal Budget", IEEE Trans. Electron Devices, vol. xx, no. x,  pp. xxxx-xxxx, in press. [ Website ] 

• M.-W. Kim, H.-J. Park, M.-K. Lee, E.-C. Yun, S.-M. Kang, D.-E. Bang, T.-H. Kil, D. Sohn, and J.-Y. Park*, "Study on the Impact of Deuterium Annealing Duration on MOSFET Performance", Semicond. Sci. Technol., vol. 40, no. 11,  pp. 1-6, Nov. 2025. [ Website ] 

Publications(KCI)

• H.-S. Jee, D. Sohn, J.-W. Yeon, T.-H. Kil, H.-J. Park, E.-C. Yun, M.-K. Lee, and J.-Y. Park*, "Fabrication of Low-Cost Physically Unclonable Function (PUF) Chip using Multiple Process Variables", Trans. Electr. Electron. Mater., Sep. 2024.

Patents

• 박준영, 손돌, 김민우, 연주원, 박효준, 이문권, 윤의철", 브이-노치 메탈 접촉 구조를 갖는 나노시트 반도체소자 및 그의 제조방법", KR 10-2025-0080331, 2025.06.18. 

Conferences

• A-Y. Kim, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, D.-E. Bang, S.-M. Kang, and J.-Y. Park, "Hetero-Gate Dielectric Structures for Reducing Ambipolar Current in Nanosheet Tunneling FETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ] 

• M.-K. Lee, H.-J. Park, E.-C. Yun, J.-W. Yeon, T.-H. Kil, M.-W. Kim, S.-J. Jeon, D.-E. Bang, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park, "Partial Trench Gate Nanosheet FETs for Enhanced ION/ IOFF Ratio", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]  

• J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, D.-E. Bang, and J.-Y. Park, "Low-Temperature Deuterium Annealing for Improved Immunity against Hot-Carrier Injection in HKMG MOSFETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]  

• T.-H. Kil, J.-W. Yeon, H.-J. Park, D.-E. Bang, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park, "Material Engineering of Inner Spacer in Nanosheet FETs to Reduce Off-State Current", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]  

• D.-E. Bang, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park, "Junction Depth Engineered Trench Gate Nanosheet FETs for Suppressing Leakage Current in Parasitic Substrate Channels", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ] 

• Y.-J. Choi, S.-M. Kang, H.-J. Park, T.-H. Kil, J.-W. Yeon, H.-S. Jee, E.-C. Yun, M.-K. Lee, D. Sohn, D.-E. Bang, A.-Y. Kim, and J.-Y. Park, "Impact of Hydrogen Passivation after Deuterium Annealing in the Fabrication of Silicon MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] "Award" [ PDF ]  

• E.-C. Yun, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, H.-S. Jee, D. Sohn, S.-M. Kang, A.-Y. Kim, Y.-J. Choi, D.-E. Bang, and  J.-Y. Park, "Spacer-Less Trench Gate Nanosheet FET for Improved On-State Current and Simplified Fabrication Process", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]  

• T.-H. Kil, H.-J. Park, J.-W. Yeon, E.-C. Yun, M.-K. Lee, D. Sohn, H.-S. Jee, S.-M. Kang, A.-Y. Kim, Y.-J. Choi, D.-E. Bang, and  J.-Y. Park, "Low-Temperature Deuterium Annealing for Enhanced Ionizing Radiation and Electrical Stress Immunity in MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]  

• D.-E. Bang, A-Y. Kim, Y.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, D. Sohn, H.-S. Jee, S.-M. Kang, Y.-J. Choi, and J.-Y. Park, "Optimization of Doping Profile for Improved Performance of Nanosheet FET", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] "Award" [ PDF ]  

• H.-S. Jee, D. Sohn, J.-W. Yeon, H.-J. Park, T.-H. Kil, E.-C. Yun, M.-K. Lee, S.-M. Kang, A.-Y. Kim, Y.-J. Choi, D.-E. Bang, and  J.-Y. Park, "Development of Physically Unclonable Function (PUF) using Multiple Process Variables", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]  "Award" [ PDF ]  

Training Experiences

• H-Mobility Class, Electrified-Track, (Apr. 21. 2025 - Jun. 13. 2025), Hyundai Motors

• Youth Hy-Po 7th, (Jun. 27. 2025 - Aug. 30. 2025), SK Hynix

Research Projects

• 고압 중수소 열처리를 통한 실리콘 MOSFET 소자의 Gate Dielectric 신뢰성 개선 (Dec. 01. 2024. -  Apr. 30. 2025), 삼성전자 

• 중수소 기반의 반도체 공정기술 및 서비스 개발 (May. 01. 2024. -  Dec. 31. 2024), 과학기술정보통신부 

Scholarship

• Graduate Student (Master) Excellence Scholarship, 2026, 과학기술정보통신부, 한국장학재단

Award

• Capstone Design : Top Award (2024.11)

Teaching Assistants

• T.A for '반도체소자공정실험' (Sep. 2025 - Dec. 2025)

Reference

• School of Semiconductor Engineering, Chung-buk National University, 1 Chungdae-ro, Seowon-gu, Cheongju, South Korea, 28644

• E-mail: junyoung@cbnu.ac.kr

• Tel: +82 - 43 - 261 - 3327