Soheil Hashemi

Welcome to my personal homepage,

I am a postdoctoral research associate at Brown University. I received my PhD. and MSc. in Electrical and Computer Engineering in 2018 and 2015 from Brown University and my BSc. degree in Electrical Engineering from Sharif University of Technology, Tehran in 2013. I currently work with Prof. Sherief Reda in SCALE lab and my primary research interests are:

• Approximate computing
• Efficient hardware realization of deep neural networks
• Low-power and embedded hardware design techniques
• Applications of Machine-learning in hardware design

You can find my latest resume here.

And my Google Scholar profile here.

Past Projects:

Power Efficient Deep Neural Networks have gained significant attention in the recent years as availability of big data is increasing. Currently state of the art neural networks require significant power and memory budget for both training and deployment. In our work, we evaluate a wide range of techniques design time and runtime techniques to reduce the footprint of deep neural networks enabling use of neural network in embedded and battery operated systems. Techniques such as modified training process, runtime channel reduction, and low-precision and low-quantization are evaluated.

Approximate Logic Synthesis can enable realization of approximate computing on a broad range of digital circuits. While, approximate arithmetic can enable significant benefits in hardware metrics, approximate logic synthesis provides a more versatile approach. In this project, we propose approximate logic synthesis enabled by non-negative matrix factorization (NNMF). More specifically, we propose to utilize NNMF to factorize the truth table of a combinational circuit into a compressor and a decompressor circuit. The circuits then can be connected together to generate the approximate design. Through extensive evaluations we show significant benefits in hardware cost while introducing insignificant errors in the output.

Approximate End-to-End Biometric Systems provide new opportunities for low-power computing, where approximate computing techniques can be utilized to lower the power consumption while providing industry standard QoS guarantees. In this project, design space exploration of an end-to-end (from camera to final signature) system for iris recognition is investigated and a novel RNN based design space exploration methodology is proposed. Implementing on a Xilinx Spartan6 FPGA board, speedups of 48x are achieved while performing within industry standard accuracy bounds.

ABACUS stands for Automated Behavioral Approximate CircUit Synthesis. This tool enables the designer to explore the approximated design space of arbitrary high-level Verilog input. ABACUS, in an automated fashion, generates optimal approximate variants of an accurate hardware, using a recursive stochastic evolutionary algorithm (based on NSGA-II algorithm). We also introduce critical path aware approximations where the tool is guided to prioritize approximations on the critical path resulting in timing slacks and therefore enabling further power savings by voltage scaling. Implementing four benchmarks our methodology can achieve up to 89% savings in both design area and power consumption at the cost of small insignificant reduction in accuracy.

Source code and more information on github repository.

Approximate Arithmetic Blocks such as adders, multipliers, and dividers can be used to approximate a wide range of combinational logic as they are the building blocks of more complex units. We investigate and propose a novel methodology for approximate multiplier and divider designs. Our methodology automatically zooms in on the most important part of each operand therefore guaranteeing a maximum error bound for the operation. Further, by selecting the important bits dynamically lower significance bits and leading zeros can be discarded resulting in significant power consumption and design area benefits.

Source code and more information on github repository.