We study next-generation oxide semiconductor thin-film transistors (TFTs) for advanced display backplanes. Our research focuses on improving device reliability, such as NB(I)S and PBS stability, through post-treatment engineering and interface analysis. In particular, we systematically characterize the impact of plasma treatment on device characteristics and quantify the passivation of oxygen vacancies and other defect states within oxide semiconductor channels

We also investigate device scaling by analyzing short-channel effects (SCE), including threshold-voltage roll-off and drain-induced barrier lowering (DIBL), as well as contact resistance issues arising in ultra-thin channels. Our group develops new device structures that suppress dopant diffusion in doped regions and improve contact resistance by inserting interlayers

We study TFTs with high subthreshold swing characteristics for potential use in high-performance display circuits. Additionally, we analyze the underlying device physics using TCAD simulations and advanced characterization techniques such as XPS, TEM and EDS

Our group develops IGZO-TFT-based devices that maintain high electrical performance under mechanical strain. By employing rigid-island structures to mechanically isolate brittle oxide semiconductors and optimizing metal interconnects and gate-insulator stacks, we develop device platforms with enhanced stretchability and reliability. We also study degradation mechanisms of stretchable IGZO TFTs under cyclic strain to guide robust device design, and explore transparent, high-reliability stretchable IGZO TFTs for image-sensor and other optoelectronic applications

To guide device architecture and material selection, we perform Finite Element Analysis (FEA) and solid-mechanics-based multiphysics simulations. These simulations are used to identify mechanically vulnerable regions, evaluate design choices, and optimize layer thicknesses and stacking sequences. Based on these analyses, we propose stress-relief structures and explore new rigid-island, interconnect, and channel geometries that mitigate mechanical stress in active devices

We are advancing Flash memory technology by utilizing IGZO as a channel material, known for its extremely low leakage current and high mobility

• Device Engineering: We optimize the gate stack structure and materials to enhance charge injection efficiency and stability

• Layout Optimization: Based on semiconductor physics, we engineer the Gate Coupling Ratio (GCR) through precise layout design to maximize program/erase efficiency

• Reliability: Our research aims to secure industrial-grade reliability metrics, specifically focusing on extending endurance cycling and improving data retention characteristics at high temperatures

We explore Ferroelectric Field-Effect Transistors (FeFETs) by integrating IGZO channels with emerging ferroelectric materials (e.g., HfO₂-based oxides). This research aims to achieve high-speed, low-power non-volatile memory solutions. Ferroelectric diodes (FeDiodes) based on nitrogen-doped oxide semiconductors such as ZnON are being developed, and their use for neuromorphic computing is also under active investigation. 

• Interface Engineering: We focus on optimizing the interface between the ferroelectric layer and the oxide semiconductor to ensure stable polarization switching and minimize leakage

• Performance Metrics: We analyze the memory window and hysteresis characteristics to overcome critical issues such as the wake-up effect and fatigue, ensuring robust device performance for next-generation memory applications

Leveraging our e-NVM devices (Flash & Ferroelectric TFTs) as synaptic components, we are developing hardware implementations of Spiking Neural Networks (SNNs), a bio-inspired architecture designed for ultra-low-power AI computation. Our research spans from device physics to system-level simulation: Device Level (characterize and optimize the synaptic plasticity and linearity of weight updates), Circuit Level (design and analyze synaptic crossbar arrays and neuron circuits to implement efficient vector-matrix multiplication operations) and System Level (conduct comprehensive neural network simulations to evaluate the classification accuracy and efficiency)

IEEE Journal of the Electron Devices Society, vol. 12 (2024)