SOGI PLL
This paper presents a ring-voltage-controlled-oscillator (ring-VCO)-based sub-sampling phase locked loop (PLL) CMOS circuit with low phase noise and low jitter. A 2.08 GHz PLL is designed and fabricated in 65 nm CMOS technology. The PLL consumes 20.4 mW while the in-band phase noise is -119.1 dBc/Hz at 1.4 MHz and the output jitter integrated from 1 kHz to 10 MHz is 0.73 ps (rms). The figure of merit (FOM) is -229.7 dB, which is the best data ever reported.
static void stringINV_dcdc_mppt_run(stringINV_dcdc_mppt_t *v) {
v->PanelPower = v->Vpv*v->Ipv;
if (v->mppt_first == 1)
{
v->VmppOut= v->Vpv -10;
v->mppt_first=0;
v->PanelPower_Prev=v->PanelPower;
}
else
{
v->PanelPower= (v->Vpv*v->Ipv);
v->DeltaP=v->PanelPower-v->PanelPower_Prev;
if (v->DeltaP > v->DeltaPmin)
{
v->VmppOut=v->Vpv+v->Stepsize;
}
else if (v->DeltaP < -v->DeltaPmin)
{
v->Stepsize=-v->Stepsize;
v->VmppOut=v->Vpv+v->Stepsize;
}
v->PanelPower_Prev = v->PanelPower;
}
if(v->VmppOut< v->MinVolt) v->VmppOut = v->MinVolt;
if(v->VmppOut> v->MaxVolt) v->VmppOut= v->MaxVolt;
}
//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
void stringX_MPPT(void){
stringINV_DCDC_mppt_counter++;
if(stringINV_DCDC_mppt_counter == stringINV_DCDC_MPPT_COUNTER_THR-2) {
stringINV_DCDC_b1_mppt_incc.Ipv = Ipv;
stringINV_DCDC_b1_mppt_incc.Vpv = Vpv;
stringINV_dcdc_mppt_run(&stringINV_DCDC_b1_mppt_incc);
stringINV_DCDC_b1_voltage_ref = stringINV_DCDC_b1_mppt_incc.VmppOut;
// stringINV_DCDC_b1_mppt_incc.mppt_first=1;
}
if(stringINV_DCDC_mppt_counter == stringINV_DCDC_MPPT_COUNTER_THR) {
stringINV_DCDC_mppt_counter = 0;
startcal++;
if(startcal==10)
{
stringINV_DCDC_b1_mppt_incc.mppt_first=1;
}
}
}
//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
void stringInverter_runISR1_lab_Boost_MPPT(){ //LAB 3
stringX_MPPT();
stringINV_DCDC_VBoost1_loop_err=-stringINV_DCDC_b1_voltage_ref+Vpv;
duty_opal = DCL_runPI_C2(&gv_VBoost_pi_1,stringINV_DCDC_VBoost1_loop_err,0);
//duty_opal=stringINV_Boost1_Duty_Ref;
duty_opal= (duty_opal > 1.0f) ? 1.0f : duty_opal;
duty_opal = (duty_opal < 0.0f) ? 0.0f : duty_opal;
}
Boost inductor:
Nanodust® Cores (alloy powder)
High Saturation Flux Density (13,000 Gauss)
Permeability from μi=26-125
CM choke:
MnZn Ferrite, μi=10.000
Bifilar common mode choke attributes:
Less differential impedance
High capacitive coupling
Less leakage inductance
Sectional common mode choke attributes:
Low capacitive coupling
High leakage inductance
Bifilar common mode choke EMC applications:
Data lines
Sensor lines
USB
HDMI
Sectional common mode choke EMC applications:
Power supply input/output filter
Switching power supply decoupling
Reference link. (Design Challenges and Considerations of Wolfspeed 22kW High Efficiency Bi-directional DCDC Converter, page 32)
Keep the sensitive signals far away from the high magnetic field such as PFC choke, DCDC power magnetics.
Small pad size of Drain nodes to reduce the coupling and parasitic capacitance
Keep the sensitive signals far away from the high dV/dt trace/nodes.
Short and small traces to reduce the coupling and parasitic capacitance.
Short trace reduces the voltage spike due to parasitic inductance.
Place ceramic or film caps as close as possible to minimize the high frequency di/dt loop.
Proper PCB layout of the power components to minimize the high frequency di/dt loop.
Avoid overlap between Gate, Gate drive circuit, bias power supply for Gate drive and the drain of the MOSFET.
Minimized the loop of gate drive
Minimized the loop of active miller clamp
Separated gate source. Don’t introduce parasitic inductance from power source loop
Place the external Gate to Source cap as close as possible to the MOSFET