Projects

Project 1

Design of a PMOS Telescopic Operational Amplifier to be used in non-inverting configuration

Associated with: Indian Institute of Technology, Kanpur, (Analog VLSI Circuits: EE610A)

(Prof. Imon Mondal)

Description: The Differential Pair was designed with PMOS transistors as the driver circuitry for the designed topology, and to set to a specified loop-gain and -3dB closed-loop bandwidth the active load was modeled as a high swing cascode current mirror load. The topology was designed on a 180nm PDK with a supply voltage of 1.8 Volts. The aim of the project was to have the amplifier working at the possible ambient conditions. Differential OL gain at room temperature was around 58dB at DC with a CMRR of around 85dB and closed-loop bandwidth of 59MHz.

Project 2

Design of a Low Power wide-band GaAs LNA using distributed components in the sub-6GHz band

Associated with: Indian Institute of Technology, Kanpur, (RF Microelectronics: EE698F)

(Prof. Yogesh Chauhan)

Description: The LNA was designed in the frequency band of operation 2.5 - 3.5 GHz, with an optimal small signal gain (>16dB) and a minimum noise figure (<1dB) for the entire band of frequencies. The amplifier was designed for having unconditional stability up to 10GHz with a return loss of 12dB.

Project 1

Design of a BCD based ALU Block

Associated with: Indian Institute of Technology, Kanpur, (VLSI System Design: EE619A)

(Prof. Rik Dey)

Description: Design of an Arithmetic and Logical Unit (ALU) block for computing addition and subtraction on positive and negative numbers in signed magnitude form of 5 and 12 bits. The gate-level minimized circuit was designed on 'Logic Friday' software tool and the simulation (behavioral and structural modeling) was performed on Icarus Verilog simulator using Verilog HDL

Project 2

Design of a Low-Drop-out (LDO) Regulator

Associated with: Indian Institute of Technology, Kanpur, (High Frequency Analog Circuits : EE613A)

(Prof. Imon Mondal)

Description: LDO was designed to have a DC Gain of 60dB and load current varying from 0.1mA to 100mA to give out a stabilized output voltage of 0.8V for a given supply of 1V on a 45nm TSMC technology node. The load capacitance as a design constraint was given as 100pF

Project 3

Design of a 4-bit Flash Analog-to-Digital Converter

Associated with: Indian Institute of Technology, Kanpur, (Mixed-Signal IC Design : EE698I)

(Prof. R S Ashwin Kumar)

Description: Design of a 4-bit fully-differential Flash ADC with a Strong-Arm latch comparator, for a sampling rate of 60Ksps and minimum dynamic offset at a supply voltage of 0.9V, on 32nm TSMC technology node

Project 4

Design of a Delay Locked Loop

Associated with: Indian Institute of Technology, Kanpur, (Circuit Design for Frequency and Phase Synthesis : EE698G)

(Prof. Chithra)

Description: Implementation of a DLL with current-starved delay line and drain switched charge pump topologies for the reference frequency range of 500MHz to 600MHz and with a maximum tolerable offset of 100ps for supply variations ranging from 0.95V to 1.05V, on 45nm TSMC technology node

Project 5

Design of a Two-stage Fully Differential Amplifier

Associated with: Indian Institute of Technology, Kanpur, (High Frequency Analog Circuits : EE613A)

(Prof. Imon Mondal)

Description: Two-stage fully-differential amplifier with common-mode feedback circuit for each stage was designed to achieve the following specifications of :

(i) (min) DC loop gain of 50dB

(ii) (min) Unity Loop gain bandwidth of 200MHz

(iii) (min) Phase margin of 70 degrees for each loop

at 1V supply voltage and given load of 4pF and 1KOhm, on 45nm TSMC technology node