Publications

This article presents a fully integrated low-intermediate frequency (IF) receiver, Dhruva, for global navigation satellite system (GNSS). The compact receiver uniquely features a fully programmable IP with no external components and no change in the on-chip hardware for various GNSS signals (civilian and precise positioning). The receiver bandwidth is programmable from 2 to 24 MHz for signals around L1, L2, L5, and S frequency bands from Navigation with Indian Constellation (NavIC), global positioning system (GPS), Galileo, and BeiDou. A single-to-differential wideband input-matched noise-canceling low-noise amplifier (LNA) is proposed to avoid the external balun and matching components. An on-chip fractional- N phase-locked loop (PLL) with a single voltage-controlled oscillator (VCO) generates the required local oscillator (LO) frequencies. A dc offset correction circuit is proposed in the variable gain amplifier (VGA) to avoid signal saturation. Fabricated in 65-nm CMOS technology, the receiver draws a current of 38.35 mA from a 1.2-V supply while providing a maximum gain of 101.72 dB with a programmable gain of 53.53 dB and a minimum noise figure (NF) of 3.8 dB. The receiver occupies an active die area of 1.96 mm2, including the I/O padring with ESD protection.

This paper presents an analog-assisted digital low dropout (LDO) voltage regulator for implantable medical devices (IMD). In parallel to the digital loop, a low-power, subthreshold transistor-based amplifier is used to improve the transient behavior of the regulator. To improve the tracking speed and steady-state behavior of the digital loop, a segmented array architecture is employed. For overshoot and undershoot detection in the regulator output, a single reference, dynamic window detector circuit is proposed that consumes zero static power. A 0.5 μW, subthreshold CMOS voltage reference is proposed in this work operates with 0.9 V minimum power supply voltage. The measured output voltage of the regulator is 1.11 V with PSRR of 26.4 dB at 10 kHz. Fabricated in a 65-nm CMOS process, the voltage regulator occupies a die area of 0.104 mm2 including the voltage reference and the window detector circuit.

After the COVID-19 outbreak, it has been absolutely important at mass gatherings and events to check the body temperature of all the attendees before giving them entry to avoid the massive spread of diseases like COVID-19. In traditional temperature measurement methods, the time required is high, and some of them are non-hygienic due to the involvement of contact between the temperature-measuring device and the patient. So, in this paper, we have proposed a contactless, fast, portable, and safe IR-based temperature measurement system (called ThermoMudra) for simultaneously measuring the temperature of multiple people. In the proposed approach, the Haar Cascade algorithm is used for face detection in a video stream. The device is based on the thermal imaging of people, which can detect elevated temperatures to prevent contact with others. The device can be connected via hotspot to any device, and an Android app is used to monitor the temperature of people in the frame. The whole system is enclosed in a 3D printed case designed keeping in mind the self-heating of devices. It is wireless, making it a feasible portable solution for mass public gatherings. The results have been validated against a standard temperature measuring device, i.e., a digital thermometer, to understand the device’s accuracy.

This paper presents a sub-lV current-mode bandgap reference (BGR) for low-supply voltage system-on-chips (SOCs). The proposed BGR uses an amplifier with input butter to relax the biasing requirements of the transistors, avoiding the native transistors and low-threshold devices. Fabricated in standard 65 nm CMOS technology, the circuit occupies an area of 0.02 mm2 . The BGR provides an output reference voltage of 571 mV while operating with a low supply voltage of 1.04 V. Integrated into a receiver operating at 1.2 V power supply, the BGR consumes a current of 182.3 μA. The BGR exhibits a temperature coefficient of 12.34 ppm/C, power supply rejection ratio (PSRR) of 34.94 dB at 10 Hz, and an output noise voltage of 42.63 μV/√Hz at frequency close to DC in simulations.

This paper presents a compact fully integrated low-IF reconfigurable receiver for satellite navigation systems that use L1, L2, L5, and S frequency bands with 2–4 MHz signal bandwidth. A new wideband input-matched balun Low-Noise amplifier (LNA) with noise cancellation is used to avoid external matching. A new DC offset correction circuit is designed in the Variable Gain Amplifier (VGA) to avoid signal saturation. A single fully integrated on-chip Fractional-N Phase-Locked Loop (PLL) is designed to generate the local oscillator (LO) for all the frequency bands. The receiver is fabricated in 65 nm CMOS technology, and it provides a maximum gain of 101 dB with gain dynamic range of 51 dB. It achieves a minimum noise figure of 3.8 dB and an image rejection ratio (IMRR) of 28 dB. It draws a current of 34.2-42 mA from a 1.2 V supply while occupying an active die area of 1.96 mm 2 . The die is packaged in a 32-pin QFN package.

This paper presents a baseband architecture consisting of a complex IQ bandpass filter followed by a 3-stage Variable Gain Amplifier (VGA) designed for multi-standard navigation receivers. A new dc offset correction circuit based on a low-pass feedback network is proposed for high gain VGA to cancel its own dc offset and that of the previous stage. The presented baseband circuits are incorporated into a multi-standard navigation receiver fabricated in 65 nm CMOS technology. The filter and VGA together provide a programmable gain of 43 dB over a tunable bandwidth of 2-4 MHz with less than 1-dB in-band attenuation. Occupying 0.39 mm2 on-chip area, the filter and VGA draw a maximum current of 7 mA from a 1.2-V supply

Perturb and Observe (P&O) technique is the most investigated and matured approach for MPPT. However, MPPT systems based on P&O algorithm suffers from a trade-off between steady-state oscillations and tracking speed. Available adaptive perturb and observe (AP&O) algorithms increase the system’s computational complexity because of the differentiation and divisions involved. This paper discussed various AP&O algorithms and presents simulation and experimental proof of concept for a new division-less adaptive algorithm with step size directly proportional to the change in power, eliminating the complex computations. The proposed algorithm is found to be superior than conventional P&O in both steady-state and dynamic performance.