TRNGs
Digital Twins
Spiking Neurons
VLSI
Stochastic Computing
VLSI Lab Director and Ph.D. Supervisor
Magdy Bayoumi (Life Fellow, IEEE) received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Giza, Egypt, in 1973 and 1977, respectively, the M.Sc. degree in computer engineering from Washington University in St. Louis, St. Louis, MO, USA, in 1980, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada, in 1984.
He is currently the Department Head of the Electrical and Computer Engineering Department, University of Louisiana at Lafayette, Lafayette, LA, USA. His current research interests include very-large-scale integration (VLSI) design and architectures, digital signal processing (DSP), and wireless ad hoc and sensor networks.
Dr. Bayoumi was a recipient of the IEEE Circuits and Systems Society Education Award, in 2003, and the 2009 IEEE Circuits and Systems Meritorious Service Award. Also, Dr. Bayoumi was the Vice President for Conferences of the IEEE Circuits and Systems Society.
VLSI Research Group
Left to Right: Mohamed Ghoneim, Shelby Williams, Sujan Howlader, Dr. Kasem Khalil,
Dr. Magdy Bayoumi, Dr. Sara Alahmadi, Ghada Alsolami, Sonia Akter, Prosen Kirtonia and Gabriel Roy
Some of the papers on the subjects that I am reading is listed below:
(1) An Ultrahigh-Throughput and FPGA-Compatible TRNG Based on Dynamic Hybrid Metastability and Jitter Entropy Cells (2025) - Link
(2) A True Random Number Generator Based on Spin Torque Nano-Oscillator and Phase Locked Loop (2025) - Link
(3) High throughput true random number generator based on dynamically superimposed hybrid entropy sources (2025) - Link
(4) Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL (2025) - Link
(5) Design of a Novel TRNG Based on MSFRO and STR Entropy Source (2024) - Link
(6) Lightweight Hybrid Entropy Source True Random Number Generator Based on Jitter and Metastability (2024) - Link
(1) Advancing Conservation Methods of the Great Wall Cultural Heritage through Digital Twin (2025) - Link
(2) Escape the Traffic Gridlock: Digital Twins and the Future of Traffic Management (2025) - Link
(3) Foundational Research Gaps and Future Directions for Digital Twins (2024) - Link
(1) Neuron Circuit Design and Signal Integrity Analysis of a Large-scale Memristor-based Crossbar Array (2025) - Link
(2) SpikeNAS-Bench: Benchmarking NAS Algorithms for Spiking Neural Network Architecture (2025) - Link
(1) A Two-Stage CMOS Amplifier With High Degree of Stability for All Capacitive Loads (2025) - Link
(2) VLSI Architecture Design for Compact Shortcut Denoising Autoencoder Neural Network of ECG Signal (2025) - Link
(1) SCFNNs: Stochastic Computing Fuzzy Neural Networks (2026) - Link
(2) Stochastic Computing Circuits for Nonlinear Functions Based on Multiplexers (2026) - Link