The Schedule

Opening and Welcome Cocktail

Ioana Vatajelu - TIMA Laboratory, FR

Dinner

Breakfast

Session 1 - Scan Chains and Where Do They Live

Chair: Sybille Hellebrand

Talk 1: “Design and Optimized Application of IEEE 1687 Scan Networks”, by Payam Habibi, Bremen, Germany.

Talk 2: “Dependable Reconfigurable Scan Networks”, by Natalia Lylina, Stuttgart, Germany.

Talk 3: “In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip”, by Giusy Iaria, Polito, Italy.

Break

Team Building & Brain Storming

Break

Session 2 - On Defects and Variations

Chair: Natalia Lylina

Talk 1: ”Switch-Level Simulation targeting Accurate Transition Shapes in FinFETs”, by Jan Dennis Reimer, Paderborn, Germany.

Talk 2: “On-Line Reliability Estimation of Ring Oscillator PUF”, by Sergio Vinagrero, Grenoble, France.

Talk 3: “Semi-Supervised Deep Learning for Microcontroller Performance Screening, by Nicolo Bellarmino, Polito, Italy.

Talk 4: “Density-oriented diagnostic data compression strategy for characterisation of embedded memories in Automotive Systems-on-Chip”, by Giorgio Insinga, Polito, Italy.

Dinner

Breakfast

Session 3 - Reliability, Fault Detection, and Approximate Computing

Chair: Paolo Bernardi

Talk 1: “The Effects of Approximate Communication on Interconnect Performance, Power Consumption, and Safety, by Somayeh Sadeghi-Kohan, Paderborn, Germany.

Talk 2: “ Resilience analysis of the preconditioned conjugate gradient method to approximation errors”, Alexia Kourfali, Stuttgart, Germany.

Talk 3: “A Fault Injection Framework for AI Hardware Accelerator”, by Salvatore Pappalardo, Lyon, France.

Talk 4: “ Variation-aware Test Method to Increase the Reliability of Nano-scale Devices”, by Paria Najafi-haghi, Stuttgart, Germany.

Break

Brain Storming Session

How test should evolve for quality assurance of neuromorphic hardware

Moderator: Ioana Vatajelu

Social Activities 

Yeti Challange @ Arc 2000

Gala Diner

Traditional savoyard dinner @ Bourg Saint Maurice

Breakfast

Session 4 - System-Level Test and Formal Methods

Chair: T.B.D

Talk 1: ”Maximizing Power Consumption by Exploiting Genetic Algorithms for Automatic System-Level Test Program Generation”, by Denis Schwachhofer, Stuttgart, Germany.

Talk 2: “Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods”, by Marcel Merten, Bremen, Germany.

Break

Team Building & Brain Storming

Session 5 - Silicon Lifecycle Management & System-Level Test

Chair: Somayeh Sadeghi-Kohan

Talk 1: “Optimized N-detection Pattern Generation for Small Delay Faults under Process Variations”, by Hanieh Jafarzadeh, Stuttgart, Germany.

Talk 2: “Exploring System-Level Test applications: Arcana, Fallacia and Liberations” by Francesco Angione, Polito, Italy.

Talk 3 “ATPG for System-Level Test”, by Nourhan Elhamawy, Stuttgart, Germany.

Dinner

Breakfast

Closing Remarks 

Ioana Vatajelu - TIMA Laboratory, FR